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Message-ID: <86ms9ea6n5.wl-maz@kernel.org>
Date: Tue, 08 Jul 2025 19:18:06 +0100
From: Marc Zyngier <maz@...nel.org>
To: Oliver Upton <oliver.upton@...ux.dev>, Lorenzo Pieralisi <lpieralisi@...nel.org>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Arnd Bergmann <arnd@...db.de>,
Sascha Bischoff <sascha.bischoff@....com>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Timothy Hayes <timothy.hayes@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
"Liam R. Howlett" <Liam.Howlett@...cle.com>,
Peter Maydell <peter.maydell@...aro.org>,
Mark Rutland <mark.rutland@....com>,
Jiri Slaby <jirislaby@...nel.org>,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org,
linux-pci@...r.kernel.org
Subject: Re: [PATCH v7 00/31] Arm GICv5: Host driver implementation
On Thu, 03 Jul 2025 11:24:50 +0100,
Lorenzo Pieralisi <lpieralisi@...nel.org> wrote:
>
> Implement the irqchip kernel driver for the Arm GICv5 architecture,
> as described in the GICv5 beta0 specification, available at:
>
> https://developer.arm.com/documentation/aes0070
>
> The GICv5 architecture is composed of multiple components:
>
> - one or more IRS (Interrupt Routing Service)
> - zero or more ITS (Interrupt Translation Service)
> - zero or more IWB (Interrupt Wire Bridge)
>
> The GICv5 host kernel driver is organized into units corresponding
> to GICv5 components.
>
> The GICv5 architecture defines the following interrupt types:
>
> - PPI (PE-Private Peripheral Interrupt)
> - SPI (Shared Peripheral Interrupt)
> - LPI (Logical Peripheral Interrupt)
>
> This series adds sysreg entries required to automatically generate
> GICv5 registers handling code, one patch per-register.
>
> This patch series is split into patches matching *logical* entities,
> to make the review easier.
[...]
Oliver, I've pushed out a branch with these patches at [1]. Could you
please stash it in kvmarm/next and add the KVM bits to it so that it
can all simmer in -next for a bit?
Thanks,
M.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git gic-v5-host
--
Without deviation from the norm, progress is not possible.
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