linux-kernel - [irqchip: irq/irqchip-next] arm64: Add support for GICv5 GSB barriers

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Message-ID: <175199882939.406.11217739614225079831.tip-bot2@tip-bot2>
Date: Tue, 08 Jul 2025 18:20:29 -0000
From: "irqchip-bot for Lorenzo Pieralisi" <tip-bot2@...utronix.de>
To: linux-kernel@...r.kernel.org
Cc: Marc Zyngier <maz@...nel.org>, Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Will Deacon <will@...nel.org>, Catalin Marinas <catalin.marinas@....com>,
 tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] arm64: Add support for GICv5 GSB barriers

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     e62e1e9493aa7aeba6670db6373031533a4d4ced
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/e62e1e9493aa7aeba6670db6373031533a4d4ced
Author:        Lorenzo Pieralisi <lpieralisi@...nel.org>
AuthorDate:    Thu, 03 Jul 2025 12:25:09 +02:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Tue, 08 Jul 2025 18:35:51 +01:00

arm64: Add support for GICv5 GSB barriers

The GICv5 architecture introduces two barriers instructions
(GSB SYS, GSB ACK) that are used to manage interrupt effects.

Rework macro used to emit the SB barrier instruction and implement
the GSB barriers on top of it.

Suggested-by: Marc Zyngier <maz@...nel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@...nel.org>
Reviewed-by: Marc Zyngier <maz@...nel.org>
Cc: Will Deacon <will@...nel.org>
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Marc Zyngier <maz@...nel.org>
Acked-by: Catalin Marinas <catalin.marinas@....com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-19-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@...nel.org>
---
 arch/arm64/include/asm/barrier.h |  3 +++
 arch/arm64/include/asm/sysreg.h  | 12 ++++++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 1ca947d..f5801b0 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -44,6 +44,9 @@
 						 SB_BARRIER_INSN"nop\n",	\
 						 ARM64_HAS_SB))
 
+#define gsb_ack()	asm volatile(GSB_ACK_BARRIER_INSN : : : "memory")
+#define gsb_sys()	asm volatile(GSB_SYS_BARRIER_INSN : : : "memory")
+
 #ifdef CONFIG_ARM64_PSEUDO_NMI
 #define pmr_sync()						\
 	do {							\
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index f1bb0d1..9b5fc63 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -113,10 +113,14 @@
 /* Register-based PAN access, for save/restore purposes */
 #define SYS_PSTATE_PAN			sys_reg(3, 0, 4, 2, 3)
 
-#define __SYS_BARRIER_INSN(CRm, op2, Rt) \
-	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
-
-#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
+#define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt)			\
+	__emit_inst(0xd5000000					|	\
+		    sys_insn((op0), (op1), (CRn), (CRm), (op2))	|	\
+		    ((Rt) & 0x1f))
+
+#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31)
+#define GSB_SYS_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31)
+#define GSB_ACK_BARRIER_INSN		__SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31)
 
 /* Data cache zero operations */
 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)