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Message-ID: <175199883481.406.431378584117828698.tip-bot2@tip-bot2>
Date: Tue, 08 Jul 2025 18:20:34 -0000
From: "irqchip-bot for Lorenzo Pieralisi" <tip-bot2@...utronix.de>
To: linux-kernel@...r.kernel.org
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>, Marc Zyngier <maz@...nel.org>,
 Will Deacon <will@...nel.org>, Catalin Marinas <catalin.marinas@....com>,
 tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] arm64/sysreg: Add ICH_HFGWTR_EL2

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     45d9f8e195cf1374270fedf7d1e0f697068eb49f
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/45d9f8e195cf1374270fedf7d1e0f697068eb49f
Author:        Lorenzo Pieralisi <lpieralisi@...nel.org>
AuthorDate:    Thu, 03 Jul 2025 12:25:03 +02:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Tue, 08 Jul 2025 18:35:51 +01:00

arm64/sysreg: Add ICH_HFGWTR_EL2

Add ICH_HFGWTR_EL2 register description to sysreg.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@...nel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Reviewed-by: Marc Zyngier <maz@...nel.org>
Cc: Will Deacon <will@...nel.org>
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Marc Zyngier <maz@...nel.org>
Acked-by: Catalin Marinas <catalin.marinas@....com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-13-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@...nel.org>
---
 arch/arm64/tools/sysreg | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 0202b3b..9def240 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -4452,6 +4452,21 @@ Field	1	ICC_IDRn_EL1
 Field	0	ICC_APR_EL1
 EndSysreg
 
+Sysreg	ICH_HFGWTR_EL2	3	4	12	9	6
+Res0	63:21
+Field	20	ICC_PPI_ACTIVERn_EL1
+Field	19	ICC_PPI_PRIORITYRn_EL1
+Field	18	ICC_PPI_PENDRn_EL1
+Field	17	ICC_PPI_ENABLERn_EL1
+Res0	16:7
+Field	6	ICC_ICSR_EL1
+Field	5	ICC_PCR_EL1
+Res0    4:3
+Field	2	ICC_CR0_EL1
+Res0	1
+Field	0	ICC_APR_EL1
+EndSysreg
+
 Sysreg	ICH_HCR_EL2	3	4	12	11	0
 Res0	63:32
 Field	31:27	EOIcount

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