linux-kernel - [irqchip: irq/irqchip-next] arm64/sysreg: Add ICC_PPI_HMR<n>

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Message-ID: <175199884187.406.11968839936504399891.tip-bot2@tip-bot2>
Date: Tue, 08 Jul 2025 18:20:41 -0000
From: "irqchip-bot for Lorenzo Pieralisi" <tip-bot2@...utronix.de>
To: linux-kernel@...r.kernel.org
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
 Jonathan Cameron <Jonathan.Cameron@...wei.com>, Marc Zyngier <maz@...nel.org>,
 Will Deacon <will@...nel.org>, Catalin Marinas <catalin.marinas@....com>,
 tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     4ee38cd9af9dd72ee26645e90eb26b6251ba9acb
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/4ee38cd9af9dd72ee26645e90eb26b6251ba9acb
Author:        Lorenzo Pieralisi <lpieralisi@...nel.org>
AuthorDate:    Thu, 03 Jul 2025 12:24:55 +02:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Tue, 08 Jul 2025 18:35:50 +01:00

arm64/sysreg: Add ICC_PPI_HMR<n>_EL1

Add ICC_PPI_HMR<n>_EL1 registers sysreg description.

Signed-off-by: Lorenzo Pieralisi <lpieralisi@...nel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
Reviewed-by: Marc Zyngier <maz@...nel.org>
Cc: Will Deacon <will@...nel.org>
Cc: Catalin Marinas <catalin.marinas@....com>
Cc: Marc Zyngier <maz@...nel.org>
Acked-by: Catalin Marinas <catalin.marinas@....com>
Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-5-12e71f1b3528@kernel.org
Signed-off-by: Marc Zyngier <maz@...nel.org>
---
 arch/arm64/tools/sysreg | 75 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 75 insertions(+)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 81b32f5..7f096ef 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -3024,6 +3024,81 @@ Sysreg	PMIAR_EL1	3	0	9	14	7
 Field	63:0	ADDRESS
 EndSysreg
 
+SysregFields	ICC_PPI_HMRx_EL1
+Field	63	HM63
+Field	62	HM62
+Field	61	HM61
+Field	60	HM60
+Field	59	HM59
+Field	58	HM58
+Field	57	HM57
+Field	56	HM56
+Field	55	HM55
+Field	54	HM54
+Field	53	HM53
+Field	52	HM52
+Field	51	HM51
+Field	50	HM50
+Field	49	HM49
+Field	48	HM48
+Field	47	HM47
+Field	46	HM46
+Field	45	HM45
+Field	44	HM44
+Field	43	HM43
+Field	42	HM42
+Field	41	HM41
+Field	40	HM40
+Field	39	HM39
+Field	38	HM38
+Field	37	HM37
+Field	36	HM36
+Field	35	HM35
+Field	34	HM34
+Field	33	HM33
+Field	32	HM32
+Field	31	HM31
+Field	30	HM30
+Field	29	HM29
+Field	28	HM28
+Field	27	HM27
+Field	26	HM26
+Field	25	HM25
+Field	24	HM24
+Field	23	HM23
+Field	22	HM22
+Field	21	HM21
+Field	20	HM20
+Field	19	HM19
+Field	18	HM18
+Field	17	HM17
+Field	16	HM16
+Field	15	HM15
+Field	14	HM14
+Field	13	HM13
+Field	12	HM12
+Field	11	HM11
+Field	10	HM10
+Field	9	HM9
+Field	8	HM8
+Field	7	HM7
+Field	6	HM6
+Field	5	HM5
+Field	4	HM4
+Field	3	HM3
+Field	2	HM2
+Field	1	HM1
+Field	0	HM0
+EndSysregFields
+
+Sysreg	ICC_PPI_HMR0_EL1	3	0	12	10	0
+Fields ICC_PPI_HMRx_EL1
+EndSysreg
+
+Sysreg	ICC_PPI_HMR1_EL1	3	0	12	10	1
+Fields ICC_PPI_HMRx_EL1
+EndSysreg
+
 Sysreg	ICC_ICSR_EL1	3	0	12	10	4
 Res0	63:48
 Field	47:32	IAFFID