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Message-ID: <175199884359.406.4174620902443145727.tip-bot2@tip-bot2> Date: Tue, 08 Jul 2025 18:20:43 -0000 From: "irqchip-bot for Lorenzo Pieralisi" <tip-bot2@...utronix.de> To: linux-kernel@...r.kernel.org Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>, Jonathan Cameron <Jonathan.Cameron@...wei.com>, Marc Zyngier <maz@...nel.org>, Will Deacon <will@...nel.org>, Catalin Marinas <catalin.marinas@....com>, tglx@...utronix.de Subject: [irqchip: irq/irqchip-next] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: 1bd7238dc705f07dea14040a59378e4b1be7164a Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/1bd7238dc705f07dea14040a59378e4b1be7164a Author: Lorenzo Pieralisi <lpieralisi@...nel.org> AuthorDate: Thu, 03 Jul 2025 12:24:53 +02:00 Committer: Marc Zyngier <maz@...nel.org> CommitterDate: Tue, 08 Jul 2025 18:35:50 +01:00 arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Add ICC_PPI_PRIORITY<n>_EL1 sysreg description. Signed-off-by: Lorenzo Pieralisi <lpieralisi@...nel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com> Reviewed-by: Marc Zyngier <maz@...nel.org> Cc: Will Deacon <will@...nel.org> Cc: Catalin Marinas <catalin.marinas@....com> Cc: Marc Zyngier <maz@...nel.org> Acked-by: Catalin Marinas <catalin.marinas@....com> Link: https://lore.kernel.org/r/20250703-gicv5-host-v7-3-12e71f1b3528@kernel.org Signed-off-by: Marc Zyngier <maz@...nel.org> --- arch/arm64/tools/sysreg | 83 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index fb5bddc..fc17e19 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -3024,6 +3024,89 @@ Sysreg PMIAR_EL1 3 0 9 14 7 Field 63:0 ADDRESS EndSysreg +SysregFields ICC_PPI_PRIORITYRx_EL1 +Res0 63:61 +Field 60:56 Priority7 +Res0 55:53 +Field 52:48 Priority6 +Res0 47:45 +Field 44:40 Priority5 +Res0 39:37 +Field 36:32 Priority4 +Res0 31:29 +Field 28:24 Priority3 +Res0 23:21 +Field 20:16 Priority2 +Res0 15:13 +Field 12:8 Priority1 +Res0 7:5 +Field 4:0 Priority0 +EndSysregFields + +Sysreg ICC_PPI_PRIORITYR0_EL1 3 0 12 14 0 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR1_EL1 3 0 12 14 1 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR2_EL1 3 0 12 14 2 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR3_EL1 3 0 12 14 3 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR4_EL1 3 0 12 14 4 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR5_EL1 3 0 12 14 5 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR6_EL1 3 0 12 14 6 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR7_EL1 3 0 12 14 7 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR8_EL1 3 0 12 15 0 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR9_EL1 3 0 12 15 1 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR10_EL1 3 0 12 15 2 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR11_EL1 3 0 12 15 3 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR12_EL1 3 0 12 15 4 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR13_EL1 3 0 12 15 5 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR14_EL1 3 0 12 15 6 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + +Sysreg ICC_PPI_PRIORITYR15_EL1 3 0 12 15 7 +Fields ICC_PPI_PRIORITYRx_EL1 +EndSysreg + Sysreg PMSELR_EL0 3 3 9 12 5 Res0 63:5 Field 4:0 SEL
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