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Message-ID: <094e7862-d981-4c37-8941-57b4513caf2d@intel.com>
Date: Tue, 8 Jul 2025 16:11:23 -0700
From: Dave Jiang <dave.jiang@...el.com>
To: Li Ming <ming.li@...omail.com>, dave@...olabs.net,
jonathan.cameron@...wei.com, alison.schofield@...el.com,
vishal.l.verma@...el.com, ira.weiny@...el.com, dan.j.williams@...el.com,
shiju.jose@...wei.com
Cc: andriy.shevchenko@...ux.intel.com, linux-cxl@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 2/3] cxl/edac: Fix wrong dpa checking for PPR operation
On 7/7/25 10:15 PM, Li Ming wrote:
> DPA 0 is considered invalid in cxl_do_ppr(), but per Table 8-143. "Get
> Partition Info Output Payload" in CXL r3.2 section 8.2.10.9.2.1 "Get
> Partition Info(Opcode 4100h)", it mentions that DPA 0 is a valid address
> of a CXL device. So the correct implementation should be checking if the
> DPA is in the DPA range of the CXL device rather than checking if the
> DPA is equal to 0.
>
> Fixes: be9b359e056a ("cxl/edac: Add CXL memory device soft PPR control feature")
> Signed-off-by: Li Ming <ming.li@...omail.com>
> Tested-by: Shiju Jose <shiju.jose@...wei.com>
> Reviewed-by: Shiju Jose <shiju.jose@...wei.com>
Reviewed-by: Dave Jiang <dave.jiang@...el.com>
> ---
> drivers/cxl/core/edac.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/edac.c b/drivers/cxl/core/edac.c
> index 623aaa4439c4..1cf65b1538b9 100644
> --- a/drivers/cxl/core/edac.c
> +++ b/drivers/cxl/core/edac.c
> @@ -1923,8 +1923,11 @@ static int cxl_ppr_set_nibble_mask(struct device *dev, void *drv_data,
> static int cxl_do_ppr(struct device *dev, void *drv_data, u32 val)
> {
> struct cxl_ppr_context *cxl_ppr_ctx = drv_data;
> + struct cxl_memdev *cxlmd = cxl_ppr_ctx->cxlmd;
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
>
> - if (!cxl_ppr_ctx->dpa || val != EDAC_DO_MEM_REPAIR)
> + if (!resource_contains_addr(&cxlds->dpa_res, cxl_ppr_ctx->dpa) ||
> + val != EDAC_DO_MEM_REPAIR)
> return -EINVAL;
>
> return cxl_mem_perform_ppr(cxl_ppr_ctx);
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