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Message-ID: <20250708052909.4145983-2-ryan_chen@aspeedtech.com>
Date: Tue, 8 Jul 2025 13:29:07 +0800
From: Ryan Chen <ryan_chen@...eedtech.com>
To: ryan_chen <ryan_chen@...eedtech.com>, Michael Turquette
<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Philipp Zabel
<p.zabel@...gutronix.de>, Joel Stanley <joel@....id.au>, Andrew Jeffery
<andrew@...econstruct.com.au>, Rob Herring <robh@...nel.org>, "Krzysztof
Kozlowski" <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
<linux-clk@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-aspeed@...ts.ozlabs.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, Mo Elbadry <elbadrym@...gle.com>, "Rom
Lemarchand" <romlem@...gle.com>, William Kennington <wak@...gle.com>, "Yuxiao
Zhang" <yuxiaozhang@...gle.com>, <wthai@...dia.com>, <leohu@...dia.com>,
<dkodihalli@...dia.com>, <spuranik@...dia.com>
CC: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH v12 1/3] dt-bindings: clock: ast2700: modify soc0/1 clock define
-add SOC0_CLK_AHBMUX:
add SOC0_CLK_AHBMUX for ahb clock source divide.
mpll->
ahb_mux -> div_table -> clk_ahb
hpll->
-new add clock:
SOC0_CLK_MPHYSRC: UFS MPHY clock source.
SOC0_CLK_U2PHY_REFCLKSRC: USB2.0 phy clock reference source.
SOC1_CLK_I3C: I3C clock source.
Signed-off-by: Ryan Chen <ryan_chen@...eedtech.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
include/dt-bindings/clock/aspeed,ast2700-scu.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/aspeed,ast2700-scu.h b/include/dt-bindings/clock/aspeed,ast2700-scu.h
index 63021af3caf5..bacf712e8e04 100644
--- a/include/dt-bindings/clock/aspeed,ast2700-scu.h
+++ b/include/dt-bindings/clock/aspeed,ast2700-scu.h
@@ -68,6 +68,9 @@
#define SCU0_CLK_GATE_UFSCLK 53
#define SCU0_CLK_GATE_EMMCCLK 54
#define SCU0_CLK_GATE_RVAS1CLK 55
+#define SCU0_CLK_U2PHY_REFCLKSRC 56
+#define SCU0_CLK_AHBMUX 57
+#define SCU0_CLK_MPHYSRC 58
/* SOC1 clk */
#define SCU1_CLKIN 0
@@ -159,5 +162,6 @@
#define SCU1_CLK_GATE_PORTCUSB2CLK 84
#define SCU1_CLK_GATE_PORTDUSB2CLK 85
#define SCU1_CLK_GATE_LTPI1TXCLK 86
+#define SCU1_CLK_I3C 87
#endif
--
2.34.1
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