linux-kernel - [tip: x86/platform] x86/msr-index: Add AMD workload classification MSRs

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Message-ID: <175196904073.406.7552423216674662645.tip-bot2@tip-bot2>
Date: Tue, 08 Jul 2025 10:04:00 -0000
From: "tip-bot2 for Perry Yuan" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Perry Yuan <perry.yuan@....com>,
 Mario Limonciello <mario.limonciello@....com>,
 "Borislav Petkov (AMD)" <bp@...en8.de>,
 "Gautham R. Shenoy" <gautham.shenoy@....com>, ilpo.jarvinen@...ux.intel.com,
 x86@...nel.org, linux-kernel@...r.kernel.org
Subject:
 [tip: x86/platform] x86/msr-index: Add AMD workload classification MSRs

The following commit has been merged into the x86/platform branch of tip:

Commit-ID:     a3c4f3396b82849a04ffe12584c69d340f2b8610
Gitweb:        https://git.kernel.org/tip/a3c4f3396b82849a04ffe12584c69d340f2b8610
Author:        Perry Yuan <perry.yuan@....com>
AuthorDate:    Mon, 09 Jun 2025 15:05:08 -05:00
Committer:     Borislav Petkov (AMD) <bp@...en8.de>
CommitterDate: Mon, 07 Jul 2025 19:24:58 +02:00

x86/msr-index: Add AMD workload classification MSRs

Introduce new MSR registers for AMD hardware feedback support.  They provide
workload classification and configuration capabilities.

Signed-off-by: Perry Yuan <perry.yuan@....com>
Signed-off-by: Mario Limonciello <mario.limonciello@....com>
Signed-off-by: Borislav Petkov (AMD) <bp@...en8.de>
Reviewed-by: Gautham R. Shenoy <gautham.shenoy@....com>
Acked-by: Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Link: https://lore.kernel.org/20250609200518.3616080-4-superm1@kernel.org
---
 arch/x86/include/asm/msr-index.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index b7dded3..4dbf6db 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -732,6 +732,11 @@
 #define MSR_AMD64_PERF_CNTR_GLOBAL_CTL		0xc0000301
 #define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR	0xc0000302

+/* AMD Hardware Feedback Support MSRs */
+#define MSR_AMD_WORKLOAD_CLASS_CONFIG		0xc0000500
+#define MSR_AMD_WORKLOAD_CLASS_ID		0xc0000501
+#define MSR_AMD_WORKLOAD_HRST			0xc0000502
+
 /* AMD Last Branch Record MSRs */
 #define MSR_AMD64_LBR_SELECT			0xc000010e