linux-kernel - Re: [PATCH v2 4/4] arm64: dts: allwinner: a133-liontron-h-a133l: Add Ethernet support

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Message-ID: <aG0a32kcpVC6z--Y@collins>
Date: Tue, 8 Jul 2025 15:19:27 +0200
From: Paul Kocialkowski <paulk@...-base.io>
To: Andre Przywara <andre.przywara@....com>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
	linux-gpio@...r.kernel.org, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
	Jernej Skrabec <jernej.skrabec@...il.com>,
	Samuel Holland <samuel@...lland.org>,
	Linus Walleij <linus.walleij@...aro.org>
Subject: Re: [PATCH v2 4/4] arm64: dts: allwinner: a133-liontron-h-a133l: Add
 Ethernet support

Hi Andre,

Le Tue 08 Jul 25, 00:34, Andre Przywara a écrit :
> On Mon,  7 Jul 2025 18:51:55 +0200
> Paul Kocialkowski <paulk@...-base.io> wrote:
> 
> Hi Paul,
> 
> > The Liontron H-A133L board features an Ethernet controller with a
> > JLSemi JL1101 PHY. Its reset pin is tied to the PH12 GPIO.
> > 
> > Note that the reset pin must be handled as a bus-wide reset GPIO in
> > order to let the MDIO core properly reset it before trying to read
> > its identification registers. There's no other device on the MDIO bus.
> 
> putting the PHY reset GPIO into the MDIO node is a clever solution, I
> was struggling with putting it either in the MAC or PHY node, though
> conceptually it would still belong in the latter, I think. But this
> might be a more generic problem: for most other devices we activate
> reset and clock gates *before* trying to access them, though this might
> be historically different for Ethernet PHYs.

Yes this feels a bit unusual. Unfortunately the mdio bus performs probing on
the PHYs before registering them as devices, which gives us no hope of
running driver-specific code to power the PHY up.

So the only device we can hold on to is the mdio bus. I think there was an
initial design assumption that 1 mdio bus == 1 PHY device

> > The datasheet of the PHY mentions that the reset signal must be held
> > for 1 ms to take effect. Make it 2 ms (and the same for post-delay) to
> > be on the safe side without wasting too much time during boot.
> > 
> > Signed-off-by: Paul Kocialkowski <paulk@...-base.io>
> 
> Despite the above, this looks fine, and works for me:
> 
> Reviewed-by: Andre Przywara <andre.przywara@....com>
> Tested-by: Andre Przywara <andre.przywara@....com>

Thanks for the review and test!

Paul

> Cheers,
> Andre
> 
> > ---
> >  .../sun50i-a133-liontron-h-a133l.dts          | 19 +++++++++++++++++++
> >  1 file changed, 19 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
> > index fe77178d3e33..90a50910f07b 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-liontron-h-a133l.dts
> > @@ -65,6 +65,25 @@ &ehci1 {
> >  	status = "okay";
> >  };
> >  
> > +&emac0 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&rmii0_pins>;
> > +	phy-handle = <&rmii_phy>;
> > +	phy-mode = "rmii";
> > +	status = "okay";
> > +};
> > +
> > +&mdio0 {
> > +	reset-gpios = <&pio 7 12 GPIO_ACTIVE_LOW>; /* PH12 */
> > +	reset-delay-us = <2000>;
> > +	reset-post-delay-us = <2000>;
> > +
> > +	rmii_phy: ethernet-phy@1 {
> > +		compatible = "ethernet-phy-ieee802.3-c22";
> > +		reg = <1>;
> > +	};
> > +};
> > +
> >  &mmc0 {
> >  	vmmc-supply = <&reg_dcdc1>;
> >  	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
> 

-- 
Paul Kocialkowski,

Independent contractor - sys-base - https://www.sys-base.io/
Free software developer - https://www.paulk.fr/

Expert in multimedia, graphics and embedded hardware support with Linux.

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