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Message-ID:
<DM4PR12MB615836EC3E90259F51568F56CD49A@DM4PR12MB6158.namprd12.prod.outlook.com>
Date: Wed, 9 Jul 2025 13:58:03 +0000
From: "Musham, Sai Krishna" <sai.krishna.musham@....com>
To: Bjorn Helgaas <helgaas@...nel.org>
CC: "bhelgaas@...gle.com" <bhelgaas@...gle.com>, "lpieralisi@...nel.org"
<lpieralisi@...nel.org>, "kw@...ux.com" <kw@...ux.com>, "mani@...nel.org"
<mani@...nel.org>, "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
<krzk+dt@...nel.org>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
"cassel@...nel.org" <cassel@...nel.org>, "lkp@...el.com" <lkp@...el.com>,
"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "Simek,
Michal" <michal.simek@....com>, "Gogada, Bharat Kumar"
<bharat.kumar.gogada@....com>, "Havalige, Thippeswamy"
<thippeswamy.havalige@....com>
Subject: RE: [PATCH v4 2/2] PCI: amd-mdb: Add support for PCIe RP PERST#
signal handling
[AMD Official Use Only - AMD Internal Distribution Only]
Hi Bjorn,
> -----Original Message-----
> From: Bjorn Helgaas <helgaas@...nel.org>
> Sent: Wednesday, July 9, 2025 4:53 AM
> To: Musham, Sai Krishna <sai.krishna.musham@....com>
> Cc: bhelgaas@...gle.com; lpieralisi@...nel.org; kw@...ux.com; mani@...nel.org;
> robh@...nel.org; krzk+dt@...nel.org; conor+dt@...nel.org; cassel@...nel.org;
> lkp@...el.com; linux-pci@...r.kernel.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org; Simek, Michal <michal.simek@....com>; Gogada, Bharat
> Kumar <bharat.kumar.gogada@....com>; Havalige, Thippeswamy
> <thippeswamy.havalige@....com>
> Subject: Re: [PATCH v4 2/2] PCI: amd-mdb: Add support for PCIe RP PERST#
> signal handling
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On Thu, Jun 26, 2025 at 11:19:06AM +0530, Sai Krishna Musham wrote:
> > Add support for handling the AMD Versal Gen 2 MDB PCIe Root Port PERST#
> > signal via a GPIO by parsing the new PCIe bridge node to acquire the
> > reset GPIO.
> >
> > As part of this, update the interrupt controller node parsing to use
> > of_get_child_by_name() instead of of_get_next_child(), since the PCIe
> > node now has multiple children. This ensures the correct node is
> > selected during initialization.
> >
> > Reported-by: kernel test robot <lkp@...el.com>
> > Closes: https://lore.kernel.org/oe-kbuild-all/202506241020.rPD1a2Vr-
> lkp@...el.com/
>
> Omit these tags. This kernel test robot report is basically a code
> review comment that doesn't need to be acknowledged here (the robot's
> report says:
>
> If you fix the issue in a separate patch/commit (i.e. not just a new
> version of the same patch/commit), kindly add following tags ...
>
> IIUC this is just a new version of the same patch, so doesn't need the
> tags.
>
Sure, I will omit these tags, Thanks.
> > Signed-off-by: Sai Krishna Musham <sai.krishna.musham@....com>
> > ---
> > Changes in v4:
> > - Resolve kernel test robot warning.
> > https://lore.kernel.org/oe-kbuild-all/202506241020.rPD1a2Vr-lkp@intel.com/
> > - Update commit message.
> >
> > Changes in v3:
> > - Implement amd_mdb_parse_pcie_port to parse bridge node for reset-gpios
> property.
> >
> > Changes in v2:
> > - Change delay to PCIE_T_PVPERL_MS
> >
> > v3 https://lore.kernel.org/r/20250618080931.2472366-1-
> sai.krishna.musham@....com/
> > v2 https://lore.kernel.org/r/20250429090046.1512000-1-
> sai.krishna.musham@....com/
> > v1 https://lore.kernel.org/r/20250326041507.98232-1-
> sai.krishna.musham@....com/
> > ---
> > drivers/pci/controller/dwc/pcie-amd-mdb.c | 46 ++++++++++++++++++++++-
> > 1 file changed, 45 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-amd-mdb.c
> b/drivers/pci/controller/dwc/pcie-amd-mdb.c
> > index 9f7251a16d32..f011a83550b9 100644
> > --- a/drivers/pci/controller/dwc/pcie-amd-mdb.c
> > +++ b/drivers/pci/controller/dwc/pcie-amd-mdb.c
> > @@ -18,6 +18,7 @@
> > #include <linux/resource.h>
> > #include <linux/types.h>
> >
> > +#include "../../pci.h"
> > #include "pcie-designware.h"
> >
> > #define AMD_MDB_TLP_IR_STATUS_MISC 0x4C0
> > @@ -56,6 +57,7 @@
> > * @slcr: MDB System Level Control and Status Register (SLCR) base
> > * @intx_domain: INTx IRQ domain pointer
> > * @mdb_domain: MDB IRQ domain pointer
> > + * @perst_gpio: GPIO descriptor for PERST# signal handling
> > * @intx_irq: INTx IRQ interrupt number
> > */
> > struct amd_mdb_pcie {
> > @@ -63,6 +65,7 @@ struct amd_mdb_pcie {
> > void __iomem *slcr;
> > struct irq_domain *intx_domain;
> > struct irq_domain *mdb_domain;
> > + struct gpio_desc *perst_gpio;
> > int intx_irq;
> > };
> >
> > @@ -284,7 +287,7 @@ static int amd_mdb_pcie_init_irq_domains(struct
> amd_mdb_pcie *pcie,
> > struct device_node *pcie_intc_node;
> > int err;
> >
> > - pcie_intc_node = of_get_next_child(node, NULL);
> > + pcie_intc_node = of_get_child_by_name(node, "interrupt-controller");
> > if (!pcie_intc_node) {
> > dev_err(dev, "No PCIe Intc node found\n");
> > return -ENODEV;
> > @@ -402,6 +405,34 @@ static int amd_mdb_setup_irq(struct amd_mdb_pcie
> *pcie,
> > return 0;
> > }
> >
> > +static int amd_mdb_parse_pcie_port(struct amd_mdb_pcie *pcie)
> > +{
> > + struct device *dev = pcie->pci.dev;
> > + struct device_node *pcie_port_node;
> > +
> > + pcie_port_node = of_get_next_child_with_prefix(dev->of_node, NULL, "pcie");
> > + if (!pcie_port_node) {
> > + dev_err(dev, "No PCIe Bridge node found\n");
> > + return -ENODEV;
> > + }
> > +
> > + /* Request the GPIO for PCIe reset signal and assert */
> > + pcie->perst_gpio = devm_fwnode_gpiod_get(dev,
> of_fwnode_handle(pcie_port_node),
> > + "reset", GPIOD_OUT_HIGH, NULL);
> > + if (IS_ERR(pcie->perst_gpio)) {
> > + if (PTR_ERR(pcie->perst_gpio) != -ENOENT) {
> > + of_node_put(pcie_port_node);
> > + return dev_err_probe(dev, PTR_ERR(pcie->perst_gpio),
> > + "Failed to request reset GPIO\n");
> > + }
> > + pcie->perst_gpio = NULL;
> > + }
> > +
> > + of_node_put(pcie_port_node);
> > +
> > + return 0;
> > +}
> > +
> > static int amd_mdb_add_pcie_port(struct amd_mdb_pcie *pcie,
> > struct platform_device *pdev)
> > {
> > @@ -426,6 +457,14 @@ static int amd_mdb_add_pcie_port(struct
> amd_mdb_pcie *pcie,
> >
> > pp->ops = &amd_mdb_pcie_host_ops;
> >
> > + if (pcie->perst_gpio) {
> > + mdelay(PCIE_T_PVPERL_MS);
> > +
> > + /* Deassert the reset signal */
> > + gpiod_set_value_cansleep(pcie->perst_gpio, 0);
> > + mdelay(PCIE_T_RRS_READY_MS);
> > + }
> > +
> > err = dw_pcie_host_init(pp);
> > if (err) {
> > dev_err(dev, "Failed to initialize host, err=%d\n", err);
> > @@ -444,6 +483,7 @@ static int amd_mdb_pcie_probe(struct platform_device
> *pdev)
> > struct device *dev = &pdev->dev;
> > struct amd_mdb_pcie *pcie;
> > struct dw_pcie *pci;
> > + int ret;
> >
> > pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > if (!pcie)
> > @@ -454,6 +494,10 @@ static int amd_mdb_pcie_probe(struct platform_device
> *pdev)
> >
> > platform_set_drvdata(pdev, pcie);
> >
> > + ret = amd_mdb_parse_pcie_port(pcie);
> > + if (ret)
> > + return ret;
>
> I'm not a DT expert, but doesn't this break if you run
> amd_mdb_parse_pcie_port() on a system with an existing DT that lacks
> the pcie@0,0 stanza you added to the binding in patch [1/2]?
>
> I.e., amd_mdb_parse_pcie_port() will return -ENODEV in that case, and
> the probe will now fail?
>
> It's good to add new functionality, but if the driver runs with a DT
> that doesn't describe the new functionality, it should fall back to
> the previous behavior (without the new functionality) instead of
> failing completely.
>
Thanks for the review, I'll make this change for backward compatibility
and include it in the next patch.
> > return amd_mdb_add_pcie_port(pcie, pdev);
> > }
> >
> > --
> > 2.44.1
> >
Regards,
Sai Krishna
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