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Message-ID: <898af9ea-9b90-4d1f-8e0d-a8e0686d72a7@lunn.ch>
Date: Wed, 9 Jul 2025 17:17:18 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Ioana Ciornei <ioana.ciornei@....com>
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
Shawn Guo <shawnguo@...nel.org>, Michael Walle <mwalle@...nel.org>,
Lee Jones <lee@...nel.org>, Frank Li <Frank.Li@....com>
Subject: Re: [PATCH 5/9] drivers: gpio: add QIXIS FPGA GPIO controller
> A GPIO controller has a maximum of 8 lines (all found in the same
> register). Even within the same controller, the GPIO lines' direction is
> fixed, either output or input, without the possibility to change it.
Since this is an FPGA, not silicon, is the selection of output or
input a syntheses option?
> +static const struct of_device_id qixis_cpld_gpio_of_match[] = {
> + {
> + .compatible = "fsl,lx2160ardb-fpga-gpio-sfp2",
> + .data = &lx2160ardb_sfp2_cfg,
> + },
> + {
> + .compatible = "fsl,lx2160ardb-fpga-gpio-sfp3",
> + .data = &lx2160ardb_sfp3_cfg,
> + },
> + {
> + .compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2",
> + .data = &ls1046aqds_stat_pres2_cfg,
> + },
Does the FPGA have an ID register you can read to confirm it is what
you think it is?
Or is the bitstream downloaded at boot by another driver? Can you ask
that driver what bitstream it downloaded?
Given how similar these devices are, it seems like a typ0 could give a
mostly working device which passes testing, so doing some validation
of the compatible against the actual FPGA would be nice.
Andrew
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