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Message-ID: <20250709111527.5ba9bc31@DESKTOP-0403QTC.>
Date: Wed, 9 Jul 2025 11:15:27 -0700
From: Jacob Pan <jacob.pan@...ux.microsoft.com>
To: Jason Gunthorpe <jgg@...dia.com>
Cc: Lu Baolu <baolu.lu@...ux.intel.com>, Joerg Roedel <joro@...tes.org>,
Will Deacon <will@...nel.org>, Robin Murphy <robin.murphy@....com>, Kevin
Tian <kevin.tian@...el.com>, Jann Horn <jannh@...gle.com>, Vasant Hegde
<vasant.hegde@....com>, Dave Hansen <dave.hansen@...el.com>, Alistair
Popple <apopple@...dia.com>, Peter Zijlstra <peterz@...radead.org>,
Uladzislau Rezki <urezki@...il.com>, Jean-Philippe Brucker
<jean-philippe@...aro.org>, Andy Lutomirski <luto@...nel.org>,
iommu@...ts.linux.dev, security@...nel.org, linux-kernel@...r.kernel.org,
stable@...r.kernel.org, jacob.pan@...ux.microsoft.com
Subject: Re: [PATCH 1/1] iommu/sva: Invalidate KVA range on kernel TLB flush
Hi Jason,
On Wed, 9 Jul 2025 13:27:24 -0300
Jason Gunthorpe <jgg@...dia.com> wrote:
> On Wed, Jul 09, 2025 at 08:51:58AM -0700, Jacob Pan wrote:
> > > In the IOMMU Shared Virtual Addressing (SVA) context, the IOMMU
> > > hardware shares and walks the CPU's page tables. Architectures
> > > like x86 share static kernel address mappings across all user
> > > page tables, allowing the IOMMU to access the kernel portion of
> > > these tables.
>
> > Is there a use case where a SVA user can access kernel memory in the
> > first place?
>
> No. It should be fully blocked.
>
Then I don't understand what is the "vulnerability condition" being
addressed here. We are talking about KVA range here.
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