linux-kernel - Re: [PATCH v4 2/3] spi: Add Amlogic SPISG driver

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Message-ID: <03b7abe4-95d5-44f4-96ec-989c736e58b0@amlogic.com>
Date: Wed, 9 Jul 2025 15:02:22 +0800
From: Xianwei Zhao <xianwei.zhao@...ogic.com>
To: Mark Brown <broonie@...nel.org>
Cc: Sunny Luo <sunny.luo@...ogic.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, linux-amlogic@...ts.infradead.org,
 linux-spi@...r.kernel.org, devicetree@...r.kernel.org,
 linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 2/3] spi: Add Amlogic SPISG driver

Hi Mark,
    Thanks for your advice.

On 2025/7/8 21:50, Mark Brown wrote:
> Subject:
> Re: [PATCH v4 2/3] spi: Add Amlogic SPISG driver
> From:
> Mark Brown <broonie@...nel.org>
> Date:
> 2025/7/8 21:50
> 
> To:
> Xianwei Zhao <xianwei.zhao@...ogic.com>
> CC:
> Sunny Luo <sunny.luo@...ogic.com>, Rob Herring <robh@...nel.org>, 
> Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley 
> <conor+dt@...nel.org>, linux-amlogic@...ts.infradead.org, 
> linux-spi@...r.kernel.org, devicetree@...r.kernel.org, 
> linux-kernel@...r.kernel.org
> 
> 
> 
> On Tue, Jul 08, 2025 at 06:34:02PM +0800, Xianwei Zhao wrote:
>> On 2025/7/7 21:05, Mark Brown wrote:
>>> Is it worth having a copybreak such that smaller transfers are done
>>> using PIO?  With a lot of controllers that increases performance due to
>>> the extra overhead of setting up DMA, talking to the DMA and interrupt
>>> controllers can be as expensive as directly accessing the FIFOs.
>> If the data volume of a single transfer (xfer) is small, PIO mode does offer
>> some advantages. However, since PIO requires the CPU to wait in a busy loop
>> for the transfer to complete, it continuously occupies CPU resources. As a
>> result, its advantages are not particularly significant.
> The CPU overhead tends to be higher (you can avoid some of it with a
> dead reckoning sleep), but the latency vastly improved which for many
> applications is a worthwhile advantage.  It tends to be things like
> accesses to one or two registers on a device with registers where this
> wins, 16 bytes or lower would be a common number off the top of my head.
>
>> If PIO is to be implemented, it can only handle one transfer at a time (via
>> transfer_one), and not entire messages (which consist of multiple
>> transfers). In contrast, when processing messages, the SPI controller can
>> handle the entire sequence in one go, which also provides certain benefits.
> It's probably worth adding something to the framework to be able to take
> a decision at the message level, for writes this tends to all fall out
> naturally since the write will tend to be a single transfer anyway.

I will try to add new API message_can_dma for framework, and implement 
PIO for message.