linux-kernel - Re: [PATCH] coresight: trbe: Add ISB after TRBLIMITR write

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Message-ID: <175205529062.223753.14752038288806898687.b4-ty@arm.com>
Date: Wed,  9 Jul 2025 11:02:03 +0100
From: Suzuki K Poulose <suzuki.poulose@....com>
To: Mike Leach <mike.leach@...aro.org>,
	Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
	Marc Zyngier <maz@...nel.org>,
	James Clark <james.clark@...aro.org>
Cc: Suzuki K Poulose <suzuki.poulose@....com>,
	coresight@...ts.linaro.org,
	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] coresight: trbe: Add ISB after TRBLIMITR write


On Mon, 09 Jun 2025 11:19:05 +0100, James Clark wrote:
> DEN0154 states that hardware will be allowed to ignore writes to TRB*
> registers while the trace buffer is enabled. Add an ISB to ensure that
> it's disabled before clearing the other registers.
> 
> This is purely defensive because it's expected that arm_trbe_disable()
> would be called before teardown which has the required ISB.
> 
> [...]

Applied, thanks!

[1/1] coresight: trbe: Add ISB after TRBLIMITR write
      https://git.kernel.org/coresight/c/ba3264a1

Best regards,
-- 
Suzuki K Poulose <suzuki.poulose@....com>