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Message-ID: <20250710125231.653967-1-hchauhan@ventanamicro.com> Date: Thu, 10 Jul 2025 18:22:29 +0530 From: Himanshu Chauhan <hchauhan@...tanamicro.com> To: paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org Cc: Himanshu Chauhan <hchauhan@...tanamicro.com> Subject: [PATCH v1 0/2] riscv: Introduce support for hardware break/watchpoints This patchset adds support of hardware breakpoints and watchpoints in RISC-V architecture. The framework is built on top of perf subsystem and SBI debug trigger extension. Currently following features are not supported and are in works: - Ptrace support - Single stepping - Virtualization of debug triggers The SBI debug trigger extension proposal can be found in Chapter-19 of SBI specification: https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0-rc8/riscv-sbi.pdf The Sdtrig ISA is part of RISC-V debug specification which can be found at: https://github.com/riscv/riscv-debug-spec Himanshu Chauhan (2): riscv: Add SBI debug trigger extension and function ids riscv: Introduce support for hardware break/watchpoints arch/riscv/Kconfig | 1 + arch/riscv/include/asm/hw_breakpoint.h | 320 ++++++++++++ arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/sbi.h | 29 ++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/hw_breakpoint.c | 657 +++++++++++++++++++++++++ arch/riscv/kernel/traps.c | 6 + 7 files changed, 1016 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c -- 2.45.2
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