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Message-ID: <20250710142038.1986052-4-andrei.stefanescu@oss.nxp.com>
Date: Thu, 10 Jul 2025 17:20:26 +0300
From: Andrei Stefanescu <andrei.stefanescu@....nxp.com>
To: linus.walleij@...aro.org,
brgl@...ev.pl,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
chester62515@...il.com,
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larisa.grigore@....com,
lee@...nel.org,
shawnguo@...nel.org,
s.hauer@...gutronix.de,
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Cc: linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org,
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Andrei Stefanescu <andrei.stefanescu@....nxp.com>
Subject: [PATCH v7 03/12] arm64: dts: s32g: change pinctrl node into the new mfd node
This commit will switch to the new mfd node for representing the SIUL2
hardware. The old pinctrl binding for SIUL2 will be deprecated in a
later commit since it doesn't correctly represent the hardware.
SIUL2 is now represented as an mfd device. Move the pinctrl related
properties inside the new "nxp-siul2" node. The latter one is now used
to represent the mfd device.
This change came as a result of upstream review in the following series:
https://lore.kernel.org/linux-gpio/a924bbb6-96ec-40be-9d82-a76b2ab73afd@oss.nxp.com/
https://lore.kernel.org/all/20240926143122.1385658-3-andrei.stefanescu@oss.nxp.com/
The SIUL2 module has multiple capabilities. It has support for reading
SoC information, pinctrl and GPIO. All of this functionality is part of
the same register space. The initial pinctrl driver treated the pinctrl
functionality as separate from the GPIO one. However, they do rely on
common registers and a long, detailed and specific register range list
would be required for pinctrl&GPIO (carving out the necessary memory
for each function). Moreover, in some cases this wouldn't be enough. For
example reading a GPIO's direction would require a read of the MSCR
register corresponding to that pin. This would not be possible in the
GPIO driver because all of the MSCR registers are referenced by the
pinctrl driver.
Signed-off-by: Andrei Stefanescu <andrei.stefanescu@....nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 48 +++++++++++++++++-------
arch/arm64/boot/dts/freescale/s32g3.dtsi | 48 +++++++++++++++++-------
2 files changed, 68 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index ea1456d361a3..78b0d21ff295 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -114,20 +114,18 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
- pinctrl: pinctrl@...9c240 {
- compatible = "nxp,s32g2-siul2-pinctrl";
- /* MSCR0-MSCR101 registers on siul2_0 */
- reg = <0x4009c240 0x198>,
- /* MSCR112-MSCR122 registers on siul2_1 */
- <0x44010400 0x2c>,
- /* MSCR144-MSCR190 registers on siul2_1 */
- <0x44010480 0xbc>,
- /* IMCR0-IMCR83 registers on siul2_0 */
- <0x4009ca40 0x150>,
- /* IMCR119-IMCR397 registers on siul2_1 */
- <0x44010c1c 0x45c>,
- /* IMCR430-IMCR495 registers on siul2_1 */
- <0x440110f8 0x108>;
+ pinctrl: pinctrl@...9c000 {
+ compatible = "nxp,s32g2-siul2";
+ reg = <0x4009c000 0x179c>,
+ <0x44010000 0x17b0>;
+ reg-names = "siul20", "siul21";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 102>, <&pinctrl 112 112 79>;
+ gpio-reserved-ranges = <102 10>, <123 21>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
jtag_pins: jtag-pins {
jtag-grp0 {
@@ -315,6 +313,28 @@ usdhc0-200mhz-grp4 {
<0x20c2>;
};
};
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_major: soc-major@0 {
+ reg = <0 4>;
+ };
+
+ soc_minor: soc-minor@1 {
+ reg = <1 4>;
+ };
+
+ pcie_dev_id: pcie-dev-id@2 {
+ reg = <2 4>;
+ };
+
+ serdes_presence: serdes-presence@100 {
+ reg = <100 4>;
+ };
+ };
};
edma0: dma-controller@...44000 {
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index 991dbfbfa203..769f8210d73d 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
@@ -171,20 +171,18 @@ soc@0 {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
- pinctrl: pinctrl@...9c240 {
- compatible = "nxp,s32g2-siul2-pinctrl";
- /* MSCR0-MSCR101 registers on siul2_0 */
- reg = <0x4009c240 0x198>,
- /* MSCR112-MSCR122 registers on siul2_1 */
- <0x44010400 0x2c>,
- /* MSCR144-MSCR190 registers on siul2_1 */
- <0x44010480 0xbc>,
- /* IMCR0-IMCR83 registers on siul2_0 */
- <0x4009ca40 0x150>,
- /* IMCR119-IMCR397 registers on siul2_1 */
- <0x44010c1c 0x45c>,
- /* IMCR430-IMCR495 registers on siul2_1 */
- <0x440110f8 0x108>;
+ pinctrl: pinctrl@...9c000 {
+ compatible = "nxp,s32g3-siul2", "nxp,s32g2-siul2";
+ reg = <0x4009c000 0x179c>,
+ <0x44010000 0x17b0>;
+ reg-names = "siul20", "siul21";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 102>, <&pinctrl 112 112 79>;
+ gpio-reserved-ranges = <102 10>, <123 21>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
jtag_pins: jtag-pins {
jtag-grp0 {
@@ -372,6 +370,28 @@ usdhc0-200mhz-grp4 {
<0x20c2>;
};
};
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_major: soc-major@0 {
+ reg = <0 4>;
+ };
+
+ soc_minor: soc-minor@1 {
+ reg = <1 4>;
+ };
+
+ pcie_dev_id: pcie-dev-id@2 {
+ reg = <2 4>;
+ };
+
+ serdes_presence: serdes-presence@100 {
+ reg = <100 4>;
+ };
+ };
};
edma0: dma-controller@...44000 {
--
2.45.2
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