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Message-Id: <20250710-rtc-clk-round-rate-v1-1-33140bb2278e@redhat.com>
Date: Thu, 10 Jul 2025 11:20:21 -0400
From: Brian Masney <bmasney@...hat.com>
To: Alexandre Belloni <alexandre.belloni@...tlin.com>,
Akinobu Mita <akinobu.mita@...il.com>,
Michael Turquette <mturquette@...libre.com>,
Heiko Stuebner <heiko@...ech.de>, Andrew Morton <akpm@...ux-foundation.org>,
Avi Fishman <avifishman70@...il.com>, Tomer Maimon <tmaimon77@...il.com>,
Tali Perry <tali.perry1@...il.com>, Patrick Venture <venture@...gle.com>,
Nancy Yuen <yuenn@...gle.com>, Benjamin Fair <benjaminfair@...gle.com>,
Mia Lin <mimi05633@...il.com>,
Michael McCormick <michael.mccormick@...tel.net>,
Heiko Schocher <hs@...x.de>, Parthiban Nallathambi <pn@...x.de>,
Antoniu Miclaus <antoniu.miclaus@...log.com>,
Maxime Ripard <mripard@...nel.org>, Stephen Boyd <sboyd@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-rtc@...r.kernel.org,
linux-kernel@...r.kernel.org, openbmc@...ts.ozlabs.org,
Brian Masney <bmasney@...hat.com>
Subject: [PATCH 01/15] rtc: ds1307: fix incorrect maximum clock rate
handling
When ds3231_clk_sqw_round_rate() is called with a requested rate higher
than the highest supported rate, it currently returns 0, which disables
the clock. According to the clk API, round_rate() should instead return
the highest supported rate. Update the function to return the maximum
supported rate in this case.
Fixes: 6c6ff145b3346 ("rtc: ds1307: add clock provider support for DS3231")
Signed-off-by: Brian Masney <bmasney@...hat.com>
---
drivers/rtc/rtc-ds1307.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 5efbe69bf5ca8cbc2a325cf2797afcd14f3760bf..c8a666de9cbe9163ab7e112b01b99d97c94970d3 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -1466,7 +1466,7 @@ static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
return ds3231_clk_sqw_rates[i];
}
- return 0;
+ return ds3231_clk_sqw_rates[ARRAY_SIZE(ds3231_clk_sqw_rates) - 1];
}
static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate,
--
2.50.0
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