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Message-ID: <6ebad87b-1d04-432b-82b0-928349a6c78c@quicinc.com>
Date: Thu, 10 Jul 2025 21:34:22 +0530
From: Nitin Rawat <quic_nitirawa@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
Avri Altman
<Avri.Altman@...disk.com>,
"mani@...nel.org" <mani@...nel.org>,
"James.Bottomley@...senPartnership.com"
<James.Bottomley@...senPartnership.com>,
"martin.petersen@...cle.com"
<martin.petersen@...cle.com>,
"bvanassche@....org" <bvanassche@....org>,
"avri.altman@....com" <avri.altman@....com>,
"ebiggers@...gle.com"
<ebiggers@...gle.com>,
"neil.armstrong@...aro.org"
<neil.armstrong@...aro.org>
CC: "linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>
Subject: Re: [PATCH V3 3/3] ufs: ufs-qcom: Enable QUnipro Internal Clock
Gating
On 7/10/2025 2:54 AM, Konrad Dybcio wrote:
> On 7/9/25 11:13 PM, Nitin Rawat wrote:
>>
>>
>> On 7/9/2025 10:46 AM, Avri Altman wrote:
>>>> Enable internal clock gating for QUnipro by setting the following attributes to 1
>>>> during host controller initialization:
>>>> - DL_VS_CLK_CFG
>>>> - PA_VS_CLK_CFG_REG
>>>> - DME_VS_CORE_CLK_CTRL.DME_HW_CGC_EN
>>>>
>>>> This change is necessary to support the internal clock gating mechanism in
>>>> Qualcomm UFS host controller. This is power saving feature and hence driver
>>>> can continue to function correctly despite any error in enabling these feature.
>>> Does this change offloads clock gating?
>>> i.e. no need to set UFSHCD_CAP_CLK_GATING ?
>> No , this change does not offload sw based UFS clock gating. Host controller has its own internal clock gating mechanism
>
> Does QUnipro == "the UFS controller found on Qualcomm platforms"?
yes its same. I'll update the commit text of next patch set.
It's applicable for all Qualcomm UFS Controller version.
>
> If so, please use some version of the latter name to make it more
> easily discernible
>
> Konrad
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