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Message-ID: <20250710214319.GA4015161-robh@kernel.org>
Date: Thu, 10 Jul 2025 16:43:19 -0500
From: Rob Herring <robh@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Marijn Suijten <marijn.suijten@...ainline.org>,
linux-arm-msm@...r.kernel.org, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH 1/3] dt-bindings: clock: qcom: Add SM8750 GPU clocks
On Tue, Jul 08, 2025 at 02:47:20PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>
> The SM8750 features a "traditional" GPU_CC block, much of which is
> controlled through the GMU microcontroller. Additionally, there's
> an separate GX_CC block, where the GX GDSC is moved.
>
> Add bindings to accommodate for that.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
> ---
> .../bindings/clock/qcom,sm8450-gpucc.yaml | 5 ++
> .../bindings/clock/qcom,sm8750-gxcc.yaml | 58 ++++++++++++++++++++++
> include/dt-bindings/clock/qcom,sm8750-gpucc.h | 53 ++++++++++++++++++++
> 3 files changed, 116 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
> index 02968632fb3af34d6b3983a6a24aa742db1d59b1..d1b3557ab344b071d16dba4d5c6a267b7ab70573 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
> @@ -20,6 +20,7 @@ description: |
> include/dt-bindings/clock/qcom,sm8550-gpucc.h
> include/dt-bindings/reset/qcom,sm8450-gpucc.h
> include/dt-bindings/reset/qcom,sm8650-gpucc.h
> + include/dt-bindings/reset/qcom,sm8750-gpucc.h
> include/dt-bindings/reset/qcom,x1e80100-gpucc.h
>
> properties:
> @@ -31,6 +32,7 @@ properties:
> - qcom,sm8475-gpucc
> - qcom,sm8550-gpucc
> - qcom,sm8650-gpucc
> + - qcom,sm8750-gpucc
> - qcom,x1e80100-gpucc
> - qcom,x1p42100-gpucc
>
> @@ -40,6 +42,9 @@ properties:
> - description: GPLL0 main branch source
> - description: GPLL0 div branch source
>
> + power-domains:
> + maxItems: 1
> +
> required:
> - compatible
> - clocks
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..f35839193d18b608e177b4d6561827dfa98c9aa1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8750-gxcc.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,sm8750-gxcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Graphics Clock & Reset Controller on SM8750
> +
> +maintainers:
> + - Konrad Dybcio <konradybcio@...nel.org>
> +
> +description: |
> + Qualcomm graphics clock control module provides the clocks, resets and power
> + domains on Qualcomm SoCs.
> +
> + See also::
Don't need double colon.
> + include/dt-bindings/reset/qcom,sm8750-gpucc.h
> +
> +properties:
> + compatible:
> + enum:
> + - qcom,sm8750-gxcc
> +
> + reg:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 3
You need to define what each power domain is.
> +
> + '#power-domain-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - power-domains
> + - '#power-domain-cells'
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,sm8750-gpucc.h>
> + #include <dt-bindings/power/qcom,rpmhpd.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + clock-controller@...4000 {
> + compatible = "qcom,sm8750-gxcc";
> + reg = <0x0 0x03d64000 0x0 0x6000>;
> + power-domains = <&rpmhpd RPMHPD_GFX>,
> + <&rpmhpd RPMHPD_MXC>,
> + <&gpucc GPU_CC_CX_GDSC>;
> + #power-domain-cells = <1>;
> + };
> + };
> +...
> diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..98e2f5df78740bf298c6b1065972d7e58ee81713
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
> @@ -0,0 +1,53 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
> +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
> +
> +/* GPU_CC clocks */
> +#define GPU_CC_AHB_CLK 0
> +#define GPU_CC_CB_CLK 1
> +#define GPU_CC_CX_ACCU_SHIFT_CLK 2
> +#define GPU_CC_CX_FF_CLK 3
> +#define GPU_CC_CX_GMU_CLK 4
> +#define GPU_CC_CXO_AON_CLK 5
> +#define GPU_CC_CXO_CLK 6
> +#define GPU_CC_DEMET_CLK 7
> +#define GPU_CC_DPM_CLK 8
> +#define GPU_CC_FF_CLK_SRC 9
> +#define GPU_CC_FREQ_MEASURE_CLK 10
> +#define GPU_CC_GMU_CLK_SRC 11
> +#define GPU_CC_GX_ACCU_SHIFT_CLK 12
> +#define GPU_CC_GX_ACD_AHB_FF_CLK 13
> +#define GPU_CC_GX_AHB_FF_CLK 14
> +#define GPU_CC_GX_GMU_CLK 15
> +#define GPU_CC_GX_RCG_AHB_FF_CLK 16
> +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17
> +#define GPU_CC_HUB_AON_CLK 18
> +#define GPU_CC_HUB_CLK_SRC 19
> +#define GPU_CC_HUB_CX_INT_CLK 20
> +#define GPU_CC_HUB_DIV_CLK_SRC 21
> +#define GPU_CC_MEMNOC_GFX_CLK 22
> +#define GPU_CC_PLL0 23
> +#define GPU_CC_PLL0_OUT_EVEN 24
> +#define GPU_CC_RSCC_HUB_AON_CLK 25
> +#define GPU_CC_RSCC_XO_AON_CLK 26
> +#define GPU_CC_SLEEP_CLK 27
> +
> +/* GPU_CC power domains */
> +#define GPU_CC_CX_GDSC 0
> +
> +/* GPU_CC resets */
> +#define GPU_CC_GPU_CC_CB_BCR 0
> +#define GPU_CC_GPU_CC_CX_BCR 1
> +#define GPU_CC_GPU_CC_FAST_HUB_BCR 2
> +#define GPU_CC_GPU_CC_FF_BCR 3
> +#define GPU_CC_GPU_CC_GMU_BCR 4
> +#define GPU_CC_GPU_CC_GX_BCR 5
> +#define GPU_CC_GPU_CC_XO_BCR 6
> +
> +/* GX_CC power domains */
> +#define GX_CC_GX_GDSC 0
> +
> +#endif
>
> --
> 2.50.0
>
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