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Message-ID: <175214811246.1905791.3082982718132036980.b4-ty@sntech.de>
Date: Thu, 10 Jul 2025 13:48:37 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: Andy Yan <andyshrk@....com>
Cc: Heiko Stuebner <heiko@...ech.de>,
sboyd@...nel.org,
zhangqing@...k-chips.com,
linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org,
Andy Yan <andy.yan@...k-chips.com>
Subject: Re: [PATCH] clk: rockchip: rk3568: Add PLL rate for 132MHz
On Sun, 15 Jun 2025 20:39:05 +0800, Andy Yan wrote:
> Add PLL rate for 132 MHz to allow raydium-rm67200 panel with
> 1080x1920 resolution to run at 60 fps that driven by VPLL.
>
>
Applied, thanks!
[1/1] clk: rockchip: rk3568: Add PLL rate for 132MHz
commit: 132b62280a9dbe38c627183ae7f1611de3ee0d9a
Best regards,
--
Heiko Stuebner <heiko@...ech.de>
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