linux-kernel - Re: [PATCH 2/6] MIPS: mobileye: eyeq5: add 5 I2C controller nodes

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Message-ID: <87ikjyzu37.fsf@BLaptop.bootlin.com>
Date: Fri, 11 Jul 2025 16:21:32 +0200
From: Gregory CLEMENT <gregory.clement@...tlin.com>
To: Théo Lebrun <theo.lebrun@...tlin.com>, Thomas
 Bogendoerfer
 <tsbogend@...ha.franken.de>, Vladimir Kondratiev
 <vladimir.kondratiev@...ileye.com>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>, Tawfik Bayouk
 <tawfik.bayouk@...ileye.com>, linux-mips@...r.kernel.org,
 linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, Théo Lebrun
 <theo.lebrun@...tlin.com>, Linus Walleij <linus.walleij@...aro.org>, Andi
 Shyti <andi.shyti@...nel.org>
Subject: Re: [PATCH 2/6] MIPS: mobileye: eyeq5: add 5 I2C controller nodes

Théo Lebrun <theo.lebrun@...tlin.com> writes:

> Add the SoC I2C controller nodes to the platform devicetree. Use a
> default bus frequency of 400kHz. They are AMBA devices that are matched
> on PeriphID.
>
> Set transfer timeout to 10ms instead of Linux's default of 200ms.
>

Acked-by: Gregory CLEMENT <gregory.clement@...tlin.com>

Thanks,

Gregory

> Acked-by: Linus Walleij <linus.walleij@...aro.org>
> Acked-by: Andi Shyti <andi.shyti@...nel.org>
> Signed-off-by: Théo Lebrun <theo.lebrun@...tlin.com>
> ---
>  arch/mips/boot/dts/mobileye/eyeq5.dtsi | 75 ++++++++++++++++++++++++++++++++++
>  1 file changed, 75 insertions(+)
>
> diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> index a84e6e720619ef99e1405ae6296d8bad1aa3fa23..b9b6f2684e675020d0377147a04d7ad5bfc272c1 100644
> --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
> @@ -110,6 +110,81 @@ soc: soc {
>  		ranges;
>  		compatible = "simple-bus";
>  
> +		i2c0: i2c@...000 {
> +			compatible = "mobileye,eyeq5-i2c", "arm,primecell";
> +			reg = <0 0x300000 0x0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <400000>; /* Fast mode */
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
> +			clock-names = "i2cclk", "apb_pclk";
> +			resets = <&olb 0 13>;
> +			i2c-transfer-timeout-us = <10000>;
> +			mobileye,olb = <&olb 0>;
> +		};
> +
> +		i2c1: i2c@...000 {
> +			compatible = "mobileye,eyeq5-i2c", "arm,primecell";
> +			reg = <0 0x400000 0x0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <400000>; /* Fast mode */
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
> +			clock-names = "i2cclk", "apb_pclk";
> +			resets = <&olb 0 14>;
> +			i2c-transfer-timeout-us = <10000>;
> +			mobileye,olb = <&olb 1>;
> +		};
> +
> +		i2c2: i2c@...000 {
> +			compatible = "mobileye,eyeq5-i2c", "arm,primecell";
> +			reg = <0 0x500000 0x0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <400000>; /* Fast mode */
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
> +			clock-names = "i2cclk", "apb_pclk";
> +			resets = <&olb 0 15>;
> +			i2c-transfer-timeout-us = <10000>;
> +			mobileye,olb = <&olb 2>;
> +		};
> +
> +		i2c3: i2c@...000 {
> +			compatible = "mobileye,eyeq5-i2c", "arm,primecell";
> +			reg = <0 0x600000 0x0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <400000>; /* Fast mode */
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
> +			clock-names = "i2cclk", "apb_pclk";
> +			resets = <&olb 0 16>;
> +			i2c-transfer-timeout-us = <10000>;
> +			mobileye,olb = <&olb 3>;
> +		};
> +
> +		i2c4: i2c@...000 {
> +			compatible = "mobileye,eyeq5-i2c", "arm,primecell";
> +			reg = <0 0x700000 0x0 0x1000>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <400000>; /* Fast mode */
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
> +			clock-names = "i2cclk", "apb_pclk";
> +			resets = <&olb 0 17>;
> +			i2c-transfer-timeout-us = <10000>;
> +			mobileye,olb = <&olb 4>;
> +		};
> +
>  		uart0: serial@...000 {
>  			compatible = "arm,pl011", "arm,primecell";
>  			reg = <0 0x800000 0x0 0x1000>;
>
> -- 
> 2.50.0
>

-- 
Grégory CLEMENT, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com