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Message-ID: <aHCb+nj2qb8+P5Mp@lizhi-Precision-Tower-5810>
Date: Fri, 11 Jul 2025 01:07:06 -0400
From: Frank Li <Frank.li@....com>
To: Laurentiu Palcu <laurentiu.palcu@....nxp.com>
Cc: imx@...ts.linux.dev, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, dri-devel@...ts.freedesktop.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 7/8] arm64: dts: imx943-evk: Add support for DCIF and LVDS
On Wed, Jul 09, 2025 at 03:23:26PM +0300, Laurentiu Palcu wrote:
> Add DT nodes for DCIF and LVDS in imx943.dtsi and activate them in
> imx943-evk.dts.
>
> Signed-off-by: Laurentiu Palcu <laurentiu.palcu@....nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx943-evk.dts | 126 +++++++++++++++++++
Shawn require board dts need sperate patch.
> arch/arm64/boot/dts/freescale/imx943.dtsi | 56 ++++++++-
> 2 files changed, 181 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> index c8c3eff9df1a2..e7de7ba406407 100644
> --- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
> @@ -125,6 +125,132 @@ memory@...00000 {
> reg = <0x0 0x80000000 0x0 0x80000000>;
> device_type = "memory";
> };
> +
> + hdmi-connector {
> + compatible = "hdmi-connector";
> + label = "hdmi";
> + type = "a";
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&it6263_out>;
> + };
> + };
> + };
> +};
> +
> +&dcif {
> + status = "okay";
> +};
> +
> +&ldb {
> + assigned-clocks = <&scmi_clk IMX94_CLK_LDBPLL_VCO>,
> + <&scmi_clk IMX94_CLK_LDBPLL>;
> + assigned-clock-rates = <4158000000>, <1039500000>;
> + status = "okay";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
imx94.dts already set it
Frank
> +
> + port@1 {
> + reg = <1>;
> +
> + lvds_out: endpoint {
> + remote-endpoint = <&it6263_in>;
> + };
> + };
> + };
> +};
> +
> +&lpi2c3 {
> + clock-frequency = <400000>;
> + pinctrl-0 = <&pinctrl_lpi2c3>;
> + pinctrl-names = "default";
> + status = "okay";
> +
> + pca9548_i2c3: i2c-mux@77 {
> + compatible = "nxp,pca9548";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + lvds-to-hdmi-bridge@4c {
> + compatible = "ite,it6263";
> + reg = <0x4c>;
> + data-mapping = "jeida-24";
> + reset-gpios = <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_HIGH>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + it6263_in: endpoint {
> + remote-endpoint = <&lvds_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> +
> + it6263_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> + };
> + };
> +
> + i2c@4 {
> + reg = <4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@5 {
> + reg = <5>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@6 {
> + reg = <6>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c@7 {
> + reg = <7>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> };
>
> &lpi2c3 {
> diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> index 657c81b6016f2..db00a94812e18 100644
> --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> @@ -148,7 +148,7 @@ l3_cache: l3-cache {
> };
> };
>
> - clock-ldb-pll-div7 {
> + clock_ldb_pll_div7: clock-ldb-pll-div7 {
> compatible = "fixed-factor-clock";
> #clock-cells = <0>;
> clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> @@ -173,10 +173,64 @@ dispmix_csr: syscon@...10000 {
>
> lvds_csr: syscon@...c0000 {
> compatible = "nxp,imx94-lvds-csr", "syscon";
> + #address-cells = <1>;
> + #size-cells = <1>;
> reg = <0x0 0x4b0c0000 0x0 0x10000>;
> clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> #clock-cells = <1>;
> power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> +
> + ldb: ldb@4 {
> + compatible = "fsl,imx94-ldb";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4 0x4>, <0x8 0x4>;
> + reg-names = "ldb", "lvds";
> + clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>;
> + clock-names = "ldb";
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + lvds_in: endpoint {
> + remote-endpoint = <&dcif_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> + };
> +
> + dcif: display-controller@...20000 {
> + compatible = "nxp,imx94-dcif";
> + reg = <0x0 0x4b120000 0x0 0x300000>;
> + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common", "bg_layer", "fg_layer";
> + clocks = <&scmi_clk IMX94_CLK_DISPAPB>,
> + <&scmi_clk IMX94_CLK_DISPAXI>,
> + <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> + clock-names = "apb", "axi", "pix";
> + assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
> + assigned-clock-parents = <&clock_ldb_pll_div7>;
> + power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> + nxp,blk-ctrl = <&dispmix_csr>;
> + status = "disabled";
> +
> + port {
> + dcif_out: endpoint {
> + remote-endpoint = <&lvds_in>;
> + };
> + };
> };
> };
> };
> --
> 2.46.1
>
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