linux-kernel - Re: [PATCH v4 2/2] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <c2576c2f-2e19-40e8-bfea-27cf0acdc686@ti.com>
Date: Fri, 11 Jul 2025 13:42:37 +0530
From: Harikrishna Shenoy <a0512644@...com>
To: Devarsh Thakkar <devarsht@...com>, <vkoul@...nel.org>, <kishon@...nel.org>,
        <linux-phy@...ts.infradead.org>, <linux-kernel@...r.kernel.org>
CC: <aradhya.bhatia@...ux.dev>, <s-jain1@...com>, <r-donadkar@...com>,
        <tomi.valkeinen@...asonboard.com>, <j-choudhary@...com>,
        "Shenoy,
 Harikrishna" <h-shenoy@...com>
Subject: Re: [PATCH v4 2/2] phy: cadence: cdns-dphy: Update calibration wait
 time for startup state machine

Hi Devarsh,

Thank you for the patch.

On 04/07/25 18:29, Devarsh Thakkar wrote:
> Do read-modify-write so that we re-use the characterized reset value as
> specified in TRM [1] to program calibration wait time which defines number
> of cycles to wait for after startup state machine is in bandgap enable
> state.
>
> This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's
> AM62L and J721E SoC since earlier calibration wait time was getting
> overwritten to zero value thus failing the PLL to lockup and causing
> timeout.
>
> [1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2):
> Link: https://www.ti.com/lit/pdf/spruj83
>
> Cc: stable@...r.kernel.org
> Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
> Signed-off-by: Devarsh Thakkar <devarsht@...com>


Tested-by: Harikrishna Shenoy <h-shenoy@...com>


> ---
> V4: No change
> V3:
> - Do read-modify-write to preserve reset value for calibration wait
>    time
> V2:
> Introduced this as as separate patch
>
>   drivers/phy/cadence/cdns-dphy.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
> index da8de0a9d086..24a25606996c 100644
> --- a/drivers/phy/cadence/cdns-dphy.c
> +++ b/drivers/phy/cadence/cdns-dphy.c
> @@ -30,6 +30,7 @@
>   
>   #define DPHY_CMN_SSM			DPHY_PMA_CMN(0x20)
>   #define DPHY_CMN_SSM_EN			BIT(0)
> +#define DPHY_CMN_SSM_CAL_WAIT_TIME	GENMASK(8, 1)
>   #define DPHY_CMN_TX_MODE_EN		BIT(9)
>   
>   #define DPHY_CMN_PWM			DPHY_PMA_CMN(0x40)
> @@ -410,7 +411,8 @@ static int cdns_dphy_power_on(struct phy *phy)
>   	writel(reg, dphy->regs + DPHY_BAND_CFG);
>   
>   	/* Start TX state machine. */
> -	writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
> +	reg = readl(dphy->regs + DPHY_CMN_SSM);
> +	writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
>   	       dphy->regs + DPHY_CMN_SSM);
>   
>   	ret = cdns_dphy_wait_for_pll_lock(dphy);
>