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Message-ID: <f754d2d1-689d-4681-8cdf-9e1e5daeb6f4@oss.qualcomm.com>
Date: Fri, 11 Jul 2025 12:07:17 +0200
From: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
To: Brian Masney <bmasney@...hat.com>,
Rob Clark <robin.clark@....qualcomm.com>,
Dmitry Baryshkov
<lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maxime Ripard <mripard@...nel.org>, Stephen Boyd <sboyd@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-arm-msm@...r.kernel.org,
dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/7] drm/msm/dsi_phy_10nm: convert from round_rate() to
determine_rate()
On 7/10/25 6:27 PM, Brian Masney wrote:
> The round_rate() clk ops is deprecated, so migrate this driver from
> round_rate() to determine_rate() using the Coccinelle semantic patch
> on the cover letter of this series.
>
> Signed-off-by: Brian Masney <bmasney@...hat.com>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> index af2e30f3f842a0157f161172bfe42059cabe6a8a..d9848b5849836a75f8f6b983d96f8901d06a5dd3 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
> @@ -444,21 +444,21 @@ static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
> return (unsigned long)vco_rate;
> }
>
> -static long dsi_pll_10nm_clk_round_rate(struct clk_hw *hw,
> - unsigned long rate, unsigned long *parent_rate)
> +static int dsi_pll_10nm_clk_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> {
> struct dsi_pll_10nm *pll_10nm = to_pll_10nm(hw);
>
> - if (rate < pll_10nm->phy->cfg->min_pll_rate)
> - return pll_10nm->phy->cfg->min_pll_rate;
> - else if (rate > pll_10nm->phy->cfg->max_pll_rate)
> - return pll_10nm->phy->cfg->max_pll_rate;
> - else
> - return rate;
> + if (req->rate < pll_10nm->phy->cfg->min_pll_rate)
> + req->rate = pll_10nm->phy->cfg->min_pll_rate;
> + else if (req->rate > pll_10nm->phy->cfg->max_pll_rate)
> + req->rate = pll_10nm->phy->cfg->max_pll_rate;
clamp_t() smells better for this series
Konrad
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