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Message-ID: <86cya79f0l.wl-maz@kernel.org>
Date: Fri, 11 Jul 2025 11:51:38 +0100
From: Marc Zyngier <maz@...nel.org>
To: Lorenzo Pieralisi <lpieralisi@...nel.org>
Cc: linux-pci@...r.kernel.org,	linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org,	Toan Le <toan@...amperecomputing.com>,
	Krzysztof WilczyƄski <kwilczynski@...nel.org>,	Manivannan
 Sadhasivam <mani@...nel.org>,	Rob Herring <robh@...nel.org>,	Bjorn Helgaas
 <bhelgaas@...gle.com>,	Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [PATCH v2 09/13] PCI: xgene-msi: Sanitise MSI allocation and affinity setting

On Fri, 11 Jul 2025 11:11:02 +0100,
Lorenzo Pieralisi <lpieralisi@...nel.org> wrote:
> 
> On Fri, Jul 11, 2025 at 11:55:17AM +0200, Lorenzo Pieralisi wrote:
> > On Tue, Jul 08, 2025 at 06:34:00PM +0100, Marc Zyngier wrote:
> 
> [...]
> 
> > We could use MSInRx_HWIRQ_MASK, I can update it.
> > 
> > More importantly, what code would set data->hwirq[6:4] (and
> > data->hwirq[7:7] below) ?
> 
> Forget it. It is the hwirq allocation itself that sets those bits,
> 256 HWIRQs you use the effective cpu affinity to steer the frame,
> it makes sense now.

Exactly.

> 
> I can update the code to use the mask above and merge it.
> 
> Sorry for the noise,

No worries, and thanks for looking at it!

	M.

-- 
Without deviation from the norm, progress is not possible.

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