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Message-Id: <175232759314.19062.13901247607746044271.sendpatchset@1.0.0.127.in-addr.arpa>
Date: Sat, 12 Jul 2025 15:39:53 +0200
From: Magnus Damm <damm@...nsource.se>
To: linux-renesas-soc@...r.kernel.org
Cc: robh@...nel.org,Magnus Damm <damm@...nsource.se>,geert+renesas@...der.be,devicetree@...r.kernel.org,conor+dt@...nel.org,krzk@...nel.org,linux-kernel@...r.kernel.org,wsa+renesas@...g-engineering.com,sergei.shtylyov@...il.com,p.zabel@...gutronix.de
Subject: [PATCH v2 3/4] memory: renesas-rpc-if: Add RZ/A1 and RZ/A2 support
From: Magnus Damm <damm@...nsource.se>
Add RZ/A1 and RZ/A2 compat strings to the rpc-if driver. Also make the
reset controller optional. This is because RZ/A1 does not have any reset
bits assigned to the device so there is no reset controller available.
Signed-off-by: Magnus Damm <damm@...nsource.se>
---
Changes since v1:
- New patch
Applies to next-20250710
drivers/memory/renesas-rpc-if.c | 15 ++++++++++++---
include/memory/renesas-rpc-if.h | 1 +
2 files changed, 13 insertions(+), 3 deletions(-)
--- 0001/drivers/memory/renesas-rpc-if.c
+++ work/drivers/memory/renesas-rpc-if.c 2025-07-11 03:45:25.605098312 +0900
@@ -234,7 +234,7 @@ static int rpcif_hw_init_impl(struct rpc
int ret;
if (rpc->info->type == RPCIF_RZ_G2L) {
- ret = reset_control_reset(rpc->rstc);
+ ret = rpc->rstc ? reset_control_reset(rpc->rstc) : 0;
if (ret)
return ret;
usleep_range(200, 300);
@@ -614,7 +614,7 @@ static int rpcif_manual_xfer_impl(struct
return ret;
err_out:
- if (reset_control_reset(rpc->rstc))
+ if (rpc->rstc && reset_control_reset(rpc->rstc))
dev_err(rpc->dev, "Failed to reset HW\n");
rpcif_hw_init_impl(rpc, rpc->bus_size == 2);
return ret;
@@ -1017,7 +1017,7 @@ static int rpcif_probe(struct platform_d
rpc->size = resource_size(res);
rpc->rstc = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(rpc->rstc))
- return PTR_ERR(rpc->rstc);
+ rpc->rstc = NULL;
/*
* The enabling/disabling of spi/spix2 clocks at runtime leading to
@@ -1115,7 +1115,16 @@ static const struct rpcif_info xspi_info
.type = XSPI_RZ_G3E,
};
+static const struct rpcif_info rpcif_info_rz_a = {
+ .regmap_config = &rpcif_regmap_config,
+ .impl = &rpcif_impl,
+ .type = RPCIF_RZ_A,
+ .strtim = 7,
+};
+
static const struct of_device_id rpcif_of_match[] = {
+ { .compatible = "renesas,r7s72100-rpc-if", .data = &rpcif_info_rz_a },
+ { .compatible = "renesas,r7s9210-rpc-if", .data = &rpcif_info_rz_a },
{ .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 },
{ .compatible = "renesas,r9a09g047-xspi", .data = &xspi_info_r9a09g047 },
{ .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 },
--- 0001/include/memory/renesas-rpc-if.h
+++ work/include/memory/renesas-rpc-if.h 2025-07-11 03:38:33.472749814 +0900
@@ -62,6 +62,7 @@ enum rpcif_type {
RPCIF_RCAR_GEN4,
RPCIF_RZ_G2L,
XSPI_RZ_G3E,
+ RPCIF_RZ_A,
};
struct rpcif {
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