linux-kernel - Re: [PATCH v2 1/4] dt-bindings: cpufreq: Add mediatek,mt8196-cpufreq-hw binding

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Message-ID: <fd561a8c-f1a7-41c2-a686-abc89f5fa555@collabora.com>
Date: Mon, 14 Jul 2025 16:41:30 +0200
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
To: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>,
 Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Matthias Brugger <matthias.bgg@...il.com>
Cc: kernel@...labora.com, linux-pm@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-mediatek@...ts.infradead.org,
 "Rafael J. Wysocki" <rafael@...nel.org>,
 Viresh Kumar <viresh.kumar@...aro.org>
Subject: Re: [PATCH v2 1/4] dt-bindings: cpufreq: Add
 mediatek,mt8196-cpufreq-hw binding

Il 14/07/25 16:08, Nicolas Frattaroli ha scritto:
> The MediaTek MT8196 SoC has new cpufreq hardware, with added memory
> register ranges to control Dynamic-Voltage-Frequency-Scaling.
> 
> The DVFS hardware is controlled through a set of registers referred to
> as "FDVFS"; one is a location from which a magic number is read to
> ensure DVFS should be used, the other is a region to set the desired
> target frequency that DVFS should aim towards for each performance
> domain.
> 
> Instead of working around the old binding and its already established
> meanings for the reg items, add a new binding. The FDVFS register memory
> regions are at the beginning, which allows us to easily expand this
> binding for future SoCs which may have more than 3 performance domains.
> 
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
> ---
>   .../cpufreq/mediatek,mt8196-cpufreq-hw.yaml        | 86 ++++++++++++++++++++++
>   1 file changed, 86 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..26bf21e05888646b4d1bdac95bfba0f36e037ffd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml
> @@ -0,0 +1,86 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek CPUFreq for MT8196 and related SoCs

title: MediaTek Hybrid CPUFreq for MT8196/MT6991 series SoCs

> +
> +maintainers:
> +  - Nicolas Frattaroli <nicolas.frattaroli@...labora.com>
> +
> +description:
> +  MT8196 uses CPUFreq management hardware that supports dynamic voltage
> +  frequency scaling (dvfs), and can support several performance domains.
> +
> +properties:
> +  compatible:
> +    const: mediatek,mt8196-cpufreq-hw
> +
> +  reg:
> +    items:
> +      - description: FDVFS magic number register region

As already said in the other commit, we might just be able to avoid adding the
magic number register region :-)

> +      - description: FDVFS control register region
> +      - description: OPP tables and control for performance domain 0
> +      - description: OPP tables and control for performance domain 1
> +      - description: OPP tables and control for performance domain 2
> +
> +  "#performance-domain-cells":
> +    description:
> +      Number of cells in a performance domain specifier. Must be 1.

The description is redundant and doesn't add any real information, I think you
should drop it.

Bindings maintainers, please, opinions?

> +    const: 1
> +

Everything else looks good to me.

Cheers,
Angelo

> +required:
> +  - compatible
> +  - reg
> +  - "#performance-domain-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    cpus {
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            cpu0: cpu@0 {
> +                device_type = "cpu";
> +                compatible = "arm,cortex-a720";
> +                enable-method = "psci";
> +                performance-domains = <&performance 0>;
> +                reg = <0x000>;
> +            };
> +
> +            /* ... */
> +
> +            cpu6: cpu@600 {
> +                device_type = "cpu";
> +                compatible = "arm,cortex-x4";
> +                enable-method = "psci";
> +                performance-domains = <&performance 1>;
> +                reg = <0x600>;
> +            };
> +
> +            cpu7: cpu@700 {
> +                device_type = "cpu";
> +                compatible = "arm,cortex-x925";
> +                enable-method = "psci";
> +                performance-domains = <&performance 2>;
> +                reg = <0x700>;
> +            };
> +    };
> +
> +    /* ... */
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        performance: performance-controller@...2034 {
> +            compatible = "mediatek,mt8196-cpufreq-hw";
> +            reg = <0 0xc2c2034 0 0x4>, <0 0xc220400 0 0x20>,
> +                  <0 0xc2c0f20 0 0x120>, <0 0xc2c1040 0 0x120>,
> +                  <0 0xc2c1160 0 0x120>;
> +            #performance-domain-cells = <1>;
> +        };
> +    };
>