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Message-ID: <9ee6ee78-af88-4b57-a939-30390c790972@amd.com>
Date: Mon, 14 Jul 2025 08:51:51 -0600
From: "Williams, Gregory" <gregoryw@....com>
To: Krzysztof Kozlowski <krzk@...nel.org>,
Gregory Williams <gregory.williams@....com>, ogabbay@...nel.org,
michal.simek@....com, robh@...nel.org
Cc: dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH V1 4/9] dt-bindings: soc: xilinx: Add AI engine DT binding
On 7/12/2025 1:33 AM, Krzysztof Kozlowski wrote:
> On 11/07/2025 20:33, Williams, Gregory wrote:
>>>>>> +
>>>>>> +maintainers:
>>>>>> + - Gregory Williams <gregory.williams@....com>
>>>>>> +
>>>>>> +description:
>>>>>> + The AMD AI Engine is a tile processor with many cores (up to 400) that
>>>>>> + can run in parallel. The data routing between cores is configured through
>>>>>> + internal switches, and shim tiles interface with external interconnect, such
>>>>>> + as memory or PL. One AI engine device can have multiple apertures, each
>>>>>> + has its own address space and interrupt. At runtime application can create
>>>>>> + multiple partitions within an aperture which are groups of columns of AI
>>>>>> + engine tiles. Each AI engine partition is the minimum resetable unit for an
>>>>>> + AI engine application.
>>>>>> +
>>>>>> +properties:
>>>>>> + compatible:
>>>>>> + const: xlnx,ai-engine-v2.0
>>>>>
>>>>> What does v2.0 stands for? Versioning is discouraged, unless mapping is
>>>>> well documented.
>>>>
>>>> Sure, I will remove the versioning in V2 patch.
>>>
>>> This should be specific to product, so use the actual product/model name.
>>>
>>> Is this part of a Soc? Then standard rules apply... but I could not
>>> deduce it from the descriptions or commit msgs.
>>
>> Yes this is part of an SoC. I will be more descriptive in V2 patch.
>
> Huh... so you MUST use SoC compatibles. Don't upstream things entirely
> different than everything else.
I will fix this in V2 patch.
Thanks,
Greg
>
> Best regards,
> Krzysztof
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