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Message-ID: <aHTbUuF6VI+VdQKH@intel.com>
Date: Mon, 14 Jul 2025 18:26:26 +0800
From: Chao Gao <chao.gao@...el.com>
To: Sean Christopherson <seanjc@...gle.com>
CC: <linux-coco@...ts.linux.dev>, <x86@...nel.org>, <kvm@...r.kernel.org>,
<paulmck@...nel.org>, <pbonzini@...hat.com>, <eddie.dong@...el.com>,
<kirill.shutemov@...el.com>, <dave.hansen@...el.com>,
<dan.j.williams@...el.com>, <kai.huang@...el.com>,
<isaku.yamahata@...el.com>, <elena.reshetova@...el.com>,
<rick.p.edgecombe@...el.com>, Borislav Petkov <bp@...en8.de>, Dave Hansen
<dave.hansen@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>, Ingo Molnar
<mingo@...hat.com>, "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
<linux-kernel@...r.kernel.org>, Thomas Gleixner <tglx@...utronix.de>
Subject: Re: [RFC PATCH 00/20] TD-Preserving updates
On Fri, Jul 11, 2025 at 07:06:21AM -0700, Sean Christopherson wrote:
>On Fri, Jul 11, 2025, Chao Gao wrote:
>> >2. P-SEAMLDR seamcalls (specificially SEAMRET from P-SEAMLDR) clear current
>> > VMCS pointers, which may disrupt KVM. To prevent VMX instructions in IRQ
>> > context from encountering NULL current-VMCS pointers, P-SEAMLDR
>> > seamcalls are called with IRQ disabled. I'm uncertain if NMIs could
>> > cause a problem, but I believe they won't. See more information in patch 3.
>
>NMIs shouldn't be a problem. KVM does access the current VMCS in NMI context
>(to do VMREAD(GUEST_RIP) in response to a perf NMI), but only when KVM knows the
Yes. I also think the guest NMI handler is the only case where VMREAD/VMWRITE is
done in NMI context.
>NMI occurred in KVM's run loop. So in effect, only in KVM_RUN context, which I
>gotta image is mutually exclusive with tdx_fw_write().
Just a heads-up: P-SEAMLDR may gain other functions and be called from other
code paths, but they won't interfere with the guest NMI handler or KVM_RUN
context.
>
>It'd be nice if we could make the P-SEAMLDR calls completely NMI safe, but
>practically speaking, if KVM (or any other hypervisor) is playing with the VMCS
>in arbitrary NMI handlers, then we've probably got bigger issues.
Agreed.
It's a little late to change the CPU behavior about SEAMRET, as several CPU
generations have already been shipped. Implementing new behavior would require
a new feature bit, which could complicate the host kernel code because the
kernel would need to perform save/restore VMCS conditionally based on this new
feature. So, let's pursue a hardware change unless it becomes a practical issue
for hypervisors.
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