linux-kernel - Re: [PATCH net-next 4/5] dpll: zl3073x: Add support to adjust phase

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <e1078cc6-f22e-441a-86f5-8c4c6e239f02@redhat.com>
Date: Tue, 15 Jul 2025 16:24:36 +0200
From: Ivan Vecera <ivecera@...hat.com>
To: Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org
Cc: Prathosh Satish <Prathosh.Satish@...rochip.com>,
 Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
 Jiri Pirko <jiri@...nulli.us>, "David S. Miller" <davem@...emloft.net>,
 Jakub Kicinski <kuba@...nel.org>, linux-kernel@...r.kernel.org,
 Michal Schmidt <mschmidt@...hat.com>, Petr Oros <poros@...hat.com>
Subject: Re: [PATCH net-next 4/5] dpll: zl3073x: Add support to adjust phase

On 15. 07. 25 3:12 odp., Paolo Abeni wrote:
> On 7/10/25 5:38 PM, Ivan Vecera wrote:
>> +static int
>> +zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin,
>> +					 void *pin_priv,
>> +					 const struct dpll_device *dpll,
>> +					 void *dpll_priv,
>> +					 s32 *phase_adjust,
>> +					 struct netlink_ext_ack *extack)
>> +{
>> +	struct zl3073x_dpll *zldpll = dpll_priv;
>> +	struct zl3073x_dev *zldev = zldpll->dev;
>> +	struct zl3073x_dpll_pin *pin = pin_priv;
>> +	u32 synth_freq;
>> +	s32 phase_comp;
>> +	u8 out, synth;
>> +	int rc;
>> +
>> +	out = zl3073x_output_pin_out_get(pin->id);
>> +	synth = zl3073x_out_synth_get(zldev, out);
>> +	synth_freq = zl3073x_synth_freq_get(zldev, synth);
>> +
>> +	guard(mutex)(&zldev->multiop_lock);
>> +
>> +	/* Read output configuration */
>> +	rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD,
>> +			   ZL_REG_OUTPUT_MB_MASK, BIT(out));
>> +	if (rc)
>> +		return rc;
>> +
>> +	/* Read current output phase compensation */
>> +	rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, &phase_comp);
>> +	if (rc)
>> +		return rc;
>> +
>> +	/* Value in register is expressed in half synth clock cycles */
>> +	phase_comp *= (int)div_u64(PSEC_PER_SEC, 2 * synth_freq);
> 
> Is 'synth_freq' guaranteed to be != 0 even on extreme conditions?
> Possibly a comment or an explicit check could help.

Under normal conditions (device is working and synth is enabled) this
should not happen but additional check here is reasonable to catch
unusual conditions to avoid division by zero.

Will add it.

Thanks,
Ivan