linux-kernel - Re: [PATCH v2 0/8] PCI: rzg3s-host: Add PCIe driver for Renesas RZ/G3S SoC

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Message-ID: <20250715144616.GA2458869@bhelgaas>
Date: Tue, 15 Jul 2025 09:46:16 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Claudiu <claudiu.beznea@...on.dev>,
	Manivannan Sadhasivam <mani@...nel.org>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
	geert+renesas@...der.be, magnus.damm@...il.com,
	mturquette@...libre.com, sboyd@...nel.org, p.zabel@...gutronix.de,
	linux-pci@...r.kernel.org, linux-renesas-soc@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
	john.madieu.xa@...renesas.com,
	Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
Subject: Re: [PATCH v2 0/8] PCI: rzg3s-host: Add PCIe driver for Renesas
 RZ/G3S SoC

On Fri, May 30, 2025 at 02:19:09PM +0300, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
> 
> Hi,
> 
> Series adds a PCIe driver for the Renesas RZ/G3S SoC.
> It is split as follows:
> - patch 1/8:		updates the max register offset for RZ/G3S SYSC;
> 			this is necessary as the PCIe need to setup the
> 			SYSC for proper functioning
> - patch 2/8:		adds clock, reset and power domain support for
> 			the PCIe IP
> - patches 3-4/8:	add PCIe support for the RZ/G3S SoC
> - patches 5-8/8:	add device tree support and defconfig flag
> 
> Please provide your feedback.
> 
> Merge strategy, if any:
> - patches 1-2,5-8/8 can go through the Renesas tree
> - patches 3-4/8 can go through the PCI tree
> 
> Thank you,
> Claudiu Beznea
> 
> Changes in v2:
> - dropped "of/irq: Export of_irq_count()" as it is not needed anymore
>   in this version
> - added "arm64: dts: renesas: rzg3s-smarc-som: Update dma-ranges for PCIe"
>   to reflect the board specific memory constraints
> - addressed review comments
> - updated patch "soc: renesas: rz-sysc: Add syscon/regmap support"
> - per-patch changes are described in each individual patch
> 
> Claudiu Beznea (7):
>   clk: renesas: r9a08g045: Add clocks, resets and power domain support
>     for the PCIe
>   dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the
>     PCIe IP on Renesas RZ/G3S
>   PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC
>   arm64: dts: renesas: r9a08g045s33: Add PCIe node
>   arm64: dts: renesas: rzg3s-smarc-som: Update dma-ranges for PCIe
>   arm64: dts: renesas: rzg3s-smarc: Enable PCIe
>   arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC
> 
> John Madieu (1):
>   soc: renesas: rz-sysc: Add syscon/regmap support
> 
>  .../pci/renesas,r9a08g045s33-pcie.yaml        |  202 ++
>  MAINTAINERS                                   |    8 +
>  arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi |   60 +
>  .../boot/dts/renesas/rzg3s-smarc-som.dtsi     |    5 +
>  arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi  |   11 +
>  arch/arm64/configs/defconfig                  |    1 +
>  drivers/clk/renesas/r9a08g045-cpg.c           |   19 +
>  drivers/pci/controller/Kconfig                |    7 +
>  drivers/pci/controller/Makefile               |    1 +
>  drivers/pci/controller/pcie-rzg3s-host.c      | 1686 +++++++++++++++++
>  drivers/soc/renesas/Kconfig                   |    1 +
>  drivers/soc/renesas/r9a08g045-sysc.c          |   10 +
>  drivers/soc/renesas/r9a09g047-sys.c           |   10 +
>  drivers/soc/renesas/r9a09g057-sys.c           |   10 +
>  drivers/soc/renesas/rz-sysc.c                 |   17 +-
>  drivers/soc/renesas/rz-sysc.h                 |    3 +
>  16 files changed, 2050 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml
>  create mode 100644 drivers/pci/controller/pcie-rzg3s-host.c

Where are we at with this series?

I see
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/dwc-stm32&id=5a972a01e24b278f7302a834c6eaee5bdac12843,
but also this kernel robot report at that commit:
https://lore.kernel.org/all/202506270620.sf6EApJY-lkp@intel.com/

I normally don't include branches in pci/next until we get a
"BUILD SUCCESS" report from the robot, so this branch is in limbo at
the moment.

Bjorn