linux-kernel - Re: [PATCH v2 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node

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Message-ID: <20250715215925.GA2084021-robh@kernel.org>
Date: Tue, 15 Jul 2025 16:59:25 -0500
From: Rob Herring <robh@...nel.org>
To: Manivannan Sadhasivam <mani@...nel.org>
Cc: Bjorn Helgaas <helgaas@...nel.org>,
	Bjorn Andersson <andersson@...nel.org>,
	Konrad Dybcio <konrad.dybcio@...aro.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
	Conor Dooley <conor+dt@...nel.org>,
	cros-qcom-dts-watchers@...omium.org, linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 01/21] arm64: dts: qcom: sm8250: Add PCIe bridge node

On Sun, Jan 05, 2025 at 03:46:12PM +0530, Manivannan Sadhasivam wrote:
> Hi Bjorn,
> 
> On Fri, Jan 03, 2025 at 03:05:31PM -0600, Bjorn Helgaas wrote:
> > On Thu, Mar 21, 2024 at 04:46:21PM +0530, Manivannan Sadhasivam wrote:
> > > On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge
> > > for each controller instance. Hence, add a node to represent the bridge.
> > > 
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> > > ---
> > >  arch/arm64/boot/dts/qcom/sm8250.dtsi | 30 ++++++++++++++++++++++++++++++
> > >  1 file changed, 30 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > > index 39bd8f0eba1e..fe5485256b22 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> > > @@ -2203,6 +2203,16 @@ pcie0: pcie@...0000 {
> > >  			dma-coherent;
> > >  
> > >  			status = "disabled";
> > > +
> > > +			pcie@0 {
> > > +				device_type = "pci";
> > > +				reg = <0x0 0x0 0x0 0x0 0x0>;
> > > +				bus-range = <0x01 0xff>;
> > 
> > Hi Mani, most or all of the patches in this series add this
> > "bus-range" property.  IIUC, these are all Root Ports and hence the
> > secondary/subordinate bus numbers should be programmable.
> > 
> 
> Right. It is not a functional dependency.
> 
> > If that's the case, I don't think we need to include "bus-range" in DT
> > for them, do we?
> > 
> 
> We mostly include it to silence the below bindings check for the endpoint device
> node:
> 
> Warning (pci_device_bus_num): /soc@...cie@...0000/pcie@...ifi@0: PCI bus number 1 out of range, expected (0 - 0)

The mistake is using bus number 1 instead of 0.

> DTC check is happy if the 'bus-range' property is absent in the bridge node. But
> while validating the endpoint node (if defined), it currently relies on the
> parent 'bus-range' property to verify the bus number provided in the endpoint
> 'reg' property.
> 
> I don't know else the check can verify the correctness of the endpoint bus
> number. So deferring to Rob here.

Sorry I'm late to the party, but found this from another thread 
today[1]. More details there.

You should not have 'bus-range' at all in your DT and the bus for every 
BDF address should be 0. You only need 'bus-range' if your h/w is 
broken.

Rob

[1] https://lore.kernel.org/all/CAL_Jsq+z+5_=YXiyCW1sbKDe0cjGNG7Qk=uRQ3efAFTd1J2ayQ@mail.gmail.com/

> 
> - Mani
> 
> -- 
> மணிவண்ணன் சதாசிவம்