linux-kernel - Re: [PATCH v6] clocksource/drivers/timer-clint: Add T-Head C9xx clint

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Message-ID: <CAJFTR8S=EKRG93sGYDr4tKTdmiEMdC+tyaDGh1e_n28fKr6+kg@mail.gmail.com>
Date: Tue, 15 Jul 2025 18:15:03 -0400
From: Jesse T <mr.bossman075@...il.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: linux-riscv@...ts.infradead.org, Paul Walmsley <paul.walmsley@...ive.com>, 
	Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, 
	Alexandre Ghiti <alex@...ti.fr>, Thomas Gleixner <tglx@...utronix.de>, 
	Samuel Holland <samuel.holland@...ive.com>, Conor Dooley <conor@...nel.org>, 
	Icenowy Zheng <uwu@...nowy.me>, Jisheng Zhang <jszhang@...nel.org>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v6] clocksource/drivers/timer-clint: Add T-Head C9xx clint

On Tue, Jul 15, 2025 at 6:59 AM Daniel Lezcano
<daniel.lezcano@...aro.org> wrote:
>
> On Mon, Jun 23, 2025 at 07:15:36PM -0400, Jesse Taube wrote:
> > From: Jisheng Zhang <jszhang@...nel.org>
> >
> > To use the T-HEAD C9xx clint in RISCV-M NOMMU env, we need to take
> > care two points:
> >
> > 1.The mtimecmp in T-Head C9xx clint only supports 32bit read/write,
> > implement such support.
> >
> > 2. As pointed out by commit ca7810aecdba ("lib: utils/timer: mtimer:
> > add a quirk for lacking mtime register") of opensbi:
> >
> > "T-Head developers surely have a different understanding of time CSR and
> > CLINT's mtime register with SiFive ones, that they did not implement
> > the mtime register at all -- as shown in openC906 source code, their
> > time CSR value is just exposed at the top of their processor IP block
> > and expects an external continous counter, which makes it not
> > overrideable, and thus mtime register is not implemented, even not for
> > reading. However, if CLINTEE is not enabled in T-Head's MXSTATUS
> > extended CSR, these systems still rely on the mtimecmp registers to
> > generate timer interrupts. This makes it necessary to implement T-Head
> > C9xx CLINT support in OpenSBI MTIMER driver, which skips implementing
> > reading mtime register and falls back to default code that reads time
> > CSR."
> >
> > So, we need to fall back to read time CSR instead of mtime register.
> > Add riscv_csr_time_available static key for this purpose.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> > Signed-off-by: Jesse Taube <Mr.Bossman075@...il.com>
> > ---
> > Treat this as a completely new patch, as it is mostly rewritten.
>
> [ ... ]
Yes, Jisheng Zhang was the original author, but the patch serves the same goal.
I used their code as a starting point, so I kept the sign-off and
commit description.

>
> > V5 -> V6:
> >  - Add csr_clock_next_event
> >  - Add csr_get_cycles64 to sched_clock_register
> >  - Break get_cycles64 into csr_get_cycles64 and clint_get_cycles64
> >  - Change default behavior to use CSR time register
>
> [ ... ]
>
> Any comments for these changes from the arch maintainer ?

I don't understand? Are you asking Jisheng Zhang?

>
> Thanks
>
> --
>
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> > +static int c900_clint_clock_next_event(unsigned long delta,
> > + struct clock_event_device *ce)
> > +{
> > + void __iomem *r = clint_timer_cmp +
> > + cpuid_to_hartid_map(smp_processor_id());
> > + u64 val = clint_get_cycles64() + delta;

This line should be:
u64 val = csr_get_cycles64() + delta;
I messed up when splitting csr_get_cycles64 and clint_get_cycles64

Thanks,
Jesse Taube
> > +
> > + csr_set(CSR_IE, IE_TIE);
> > + writel_relaxed(val, r);
> > + writel_relaxed(val >> 32, r + 4);
> > + return 0;
> > +}
> > +