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Message-ID: <CA+kEDGF96VbjGPBW0hWSji2eQtQU-bXjsZAaZjjUo0cvpwhBQg@mail.gmail.com>
Date: Wed, 16 Jul 2025 00:52:54 +0200
From: Jérôme de Bretagne <jerome.debretagne@...il.com>
To: rob.clark@....qualcomm.com
Cc: Dale Whinham <daleyo@...il.com>, Rob Clark <robdclark@...il.com>, 
	Abhinav Kumar <quic_abhinavk@...cinc.com>, Dmitry Baryshkov <lumag@...nel.org>, 
	Sean Paul <sean@...rly.run>, Marijn Suijten <marijn.suijten@...ainline.org>, 
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, linux-arm-msm@...r.kernel.org, 
	dri-devel@...ts.freedesktop.org, freedreno@...ts.freedesktop.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 6/9] drm/msm/dp: Work around bogus maximum link rate

On Mon, Jul 14, 2025 at 21:51, Rob Clark <rob.clark@....qualcomm.com> wrote:
>
> On Mon, Jul 14, 2025 at 10:36 AM Dale Whinham <daleyo@...il.com> wrote:
> >
> > From: Jérôme de Bretagne <jerome.debretagne@...il.com>
> >
> > The OLED display in the Surface Pro 11 reports a maximum link rate of
> > zero in its DPCD, causing it to fail to probe correctly.
> >
> > The Surface Pro 11's DSDT table contains some XML with an
> > "EDPOverrideDPCDCaps" block that defines the max link rate as 0x1E
> > (8.1Gbps/HBR3).
> >
> > Add a quirk to conditionally override the max link rate if its value
> > is zero specifically for this model.
> >
> > Signed-off-by: Jérôme de Bretagne <jerome.debretagne@...il.com>
> > Signed-off-by: Dale Whinham <daleyo@...il.com>
> > ---
> >  drivers/gpu/drm/msm/dp/dp_panel.c | 13 +++++++++++++
> >  1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
> > index 4e8ab75c771b..b2e65b987c05 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_panel.c
> > +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
> > @@ -11,6 +11,8 @@
> >  #include <drm/drm_of.h>
> >  #include <drm/drm_print.h>
> >
> > +#include <linux/dmi.h>
> > +
> >  #define DP_MAX_NUM_DP_LANES    4
> >  #define DP_LINK_RATE_HBR2      540000 /* kbytes */
> >
> > @@ -58,6 +60,17 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *msm_dp_panel)
> >         if (rc)
> >                 return rc;
> >
> > +       /*
> > +        * for some reason the ATNA30DW01-1 OLED panel in the Surface Pro 11
> > +        * reports a max link rate of 0 in the DPCD. Fix it to match the
> > +        * EDPOverrideDPCDCaps string found in the ACPI DSDT
> > +        */
> > +       if (dpcd[DP_MAX_LINK_RATE] == 0 &&
> > +           dmi_match(DMI_SYS_VENDOR, "Microsoft Corporation") &&
> > +           dmi_match(DMI_PRODUCT_NAME, "Microsoft Surface Pro, 11th Edition")) {
> > +               dpcd[1] = DP_LINK_BW_8_1;
> > +       }
>
> Not a dp expert myself, but..
>
> In drm_dp_helpers.c there is dpcd_quirk_list[].. which applies quirks
> based on the oui ("Organizational Unique ID") of the dp sink.  I think
> this would be the correct way to handle this.  Although I guess you'll
> need to add a new quirk for this.
>
> Idk if the surface pro 11 has multiple different panel options.  If so
> you defn wouldn't want to match on the DMI.
>
> BR,
> -R

Thanks Rob for the feedback, I have a working implementation
based on your suggestion with a new quirk, we will switch to it in V2.

Best,
Jérôme

> > +
> >         msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd);
> >         link_info = &msm_dp_panel->link_info;
> >         link_info->revision = dpcd[DP_DPCD_REV];
> > --
> > 2.50.1
> >

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