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Message-ID: <CAGXv+5Fz4qBO-nPJu-bq0NEJK+md9XPJPPbd46TFCMS8=LQpAA@mail.gmail.com>
Date: Tue, 15 Jul 2025 12:53:36 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: Laura Nao <laura.nao@...labora.com>
Cc: mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, matthias.bgg@...il.com,
angelogioacchino.delregno@...labora.com, p.zabel@...gutronix.de,
richardcochran@...il.com, guangjie.song@...iatek.com,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
kernel@...labora.com
Subject: Re: [PATCH v2 12/29] clk: mediatek: Add MT8196 topckgen clock support
Hi,
There's a lot of duplication in the driver.
On Tue, Jun 24, 2025 at 10:33 PM Laura Nao <laura.nao@...labora.com> wrote:
>
> Add support for the MT8196 topckgen clock controller, which provides
> muxes and dividers for clock selection in other IP blocks.
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Signed-off-by: Laura Nao <laura.nao@...labora.com>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8196-topckgen.c | 1257 ++++++++++++++++++++
> 2 files changed, 1258 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8196-topckgen.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index b1773d2bcb3d..bc0e86e20074 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -160,7 +160,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS) += clk-mt8195-vdo0.o clk-mt8195-vdo1.o
> obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
> obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) += clk-mt8195-vpp0.o clk-mt8195-vpp1.o
> obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) += clk-mt8195-wpe.o
> -obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o
> +obj-$(CONFIG_COMMON_CLK_MT8196) += clk-mt8196-apmixedsys.o clk-mt8196-topckgen.o
> obj-$(CONFIG_COMMON_CLK_MT8365) += clk-mt8365-apmixedsys.o clk-mt8365.o
> obj-$(CONFIG_COMMON_CLK_MT8365_APU) += clk-mt8365-apu.o
> obj-$(CONFIG_COMMON_CLK_MT8365_CAM) += clk-mt8365-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8196-topckgen.c b/drivers/clk/mediatek/clk-mt8196-topckgen.c
> new file mode 100644
> index 000000000000..fc0c1227dd8d
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8196-topckgen.c
> @@ -0,0 +1,1257 @@
[...]
> +static const char * const p_axi_parents[] = {
> + "clk26m",
> + "mainpll_d7_d8",
> + "mainpll_d5_d8",
> + "osc_d8",
> + "mainpll_d7_d4",
> + "mainpll_d5_d4",
> + "mainpll_d4_d4",
> + "mainpll_d7_d2"
> +};
The next two lists are the same as the one above. Please merge them
together.
> +static const char * const ufs_pextp0_axi_parents[] = {
> + "clk26m",
> + "mainpll_d7_d8",
> + "mainpll_d5_d8",
> + "osc_d8",
> + "mainpll_d7_d4",
> + "mainpll_d5_d4",
> + "mainpll_d4_d4",
> + "mainpll_d7_d2"
> +};
> +
> +static const char * const pextp1_usb_axi_parents[] = {
> + "clk26m",
> + "mainpll_d7_d8",
> + "mainpll_d5_d8",
> + "osc_d8",
> + "mainpll_d7_d4",
> + "mainpll_d5_d4",
> + "mainpll_d4_d4",
> + "mainpll_d7_d2"
> +};
> +
> +static const char * const p_fmem_sub_parents[] = {
> + "clk26m",
> + "mainpll_d5_d8",
> + "mainpll_d5_d4",
> + "osc_d4",
> + "univpll_d4_d4",
> + "mainpll_d5_d2",
> + "mainpll_d4_d2",
> + "mainpll_d6",
> + "mainpll_d5",
> + "univpll_d5",
> + "mainpll_d4"
> +};
> +
> +static const char * const ufs_pexpt0_mem_sub_parents[] = {
> + "clk26m",
> + "mainpll_d5_d8",
> + "mainpll_d5_d4",
> + "osc_d4",
> + "univpll_d4_d4",
> + "mainpll_d5_d2",
> + "mainpll_d4_d2",
> + "mainpll_d6",
> + "mainpll_d5",
> + "univpll_d5",
> + "mainpll_d4"
> +};
The next one is the same as the previous one. Please merge together.
> +static const char * const pextp1_usb_mem_sub_parents[] = {
> + "clk26m",
> + "mainpll_d5_d8",
> + "mainpll_d5_d4",
> + "osc_d4",
> + "univpll_d4_d4",
> + "mainpll_d5_d2",
> + "mainpll_d4_d2",
> + "mainpll_d6",
> + "mainpll_d5",
> + "univpll_d5",
> + "mainpll_d4"
> +};
> +
> +static const char * const p_noc_parents[] = {
> + "clk26m",
> + "mainpll_d5_d8",
> + "mainpll_d5_d4",
> + "osc_d4",
> + "univpll_d4_d4",
> + "mainpll_d5_d2",
> + "mainpll_d4_d2",
> + "mainpll_d6",
> + "mainpll_d5",
> + "univpll_d5",
> + "mainpll_d4",
> + "mainpll_d3"
> +};
> +
> +static const char * const emi_n_parents[] = {
> + "clk26m",
> + "osc_d4",
> + "mainpll_d5_d8",
> + "mainpll_d5_d4",
> + "mainpll_d4_d4",
> + "emipll1_ck"
> +};
The next one is the same as the previous one.
> +static const char * const emi_s_parents[] = {
> + "clk26m",
> + "osc_d4",
> + "mainpll_d5_d8",
> + "mainpll_d5_d4",
> + "mainpll_d4_d4",
> + "emipll1_ck"
> +};
[...]
> +static const char * const spi0_b_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "univpll_d5_d4",
> + "mainpll_d4_d4",
> + "univpll_d4_d4",
> + "mainpll_d6_d2",
> + "univpll_192m",
> + "univpll_d6_d2"
> +};
All the SPI clocks have the same set of parents. Please just have
one list.
[...]
> +static const char * const msdc30_1_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "mainpll_d6_d2",
> + "univpll_d6_d2",
> + "msdcpll_d2"
> +};
Please merge the two msdc30 parent lists.
> +static const char * const msdc30_2_parents[] = {
> + "clk26m",
> + "univpll_d6_d4",
> + "mainpll_d6_d2",
> + "univpll_d6_d2",
> + "msdcpll_d2"
> +};
> +
> +static const char * const disp_pwm_parents[] = {
> + "clk26m",
> + "osc_d32",
> + "osc_d8",
> + "univpll_d6_d4",
> + "univpll_d5_d4",
> + "osc_d4",
> + "mainpll_d4_d4"
> +};
> +
> +static const char * const usb_1p_parents[] = {
> + "clk26m",
> + "univpll_d5_d4"
> +};
The next one is the same as the previous one. Please merge together.
> +static const char * const usb_xhci_1p_parents[] = {
> + "clk26m",
> + "univpll_d5_d4"
> +};
> +
> +static const char * const usb_fmcnt_p1_parents[] = {
> + "clk26m",
> + "univpll_192m_d4"
> +};
> +
> +static const char * const i2c_p_parents[] = {
> + "clk26m",
> + "mainpll_d4_d8",
> + "univpll_d5_d4",
> + "mainpll_d4_d4",
> + "univpll_d5_d2"
> +};
All the I2C clocks have the same set of parents. Please just have
one list.
[...]
> +static const char * const tl_parents[] = {
> + "clk26m",
> + "mainpll_d7_d4",
> + "mainpll_d4_d4",
> + "mainpll_d5_d2"
> +};
The lists for the tl clocks are the same. Please merge.
[...]
> +static const char * const ssr_pka_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d4_d2",
> + "mainpll_d7",
> + "mainpll_d6",
> + "mainpll_d5"
> +};
This one and the next could be merged.
> +static const char * const ssr_dma_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d4_d2",
> + "mainpll_d7",
> + "mainpll_d6",
> + "mainpll_d5"
> +};
> +
> +static const char * const ssr_kdf_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d4_d2",
> + "mainpll_d7"
> +};
> +
> +static const char * const ssr_rng_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d5_d2",
> + "mainpll_d4_d2"
> +};
> +
> +static const char * const spu0_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d4_d2",
> + "mainpll_d7",
> + "mainpll_d6",
> + "mainpll_d5"
> +};
This one and the next could be merged.
> +static const char * const spu1_parents[] = {
> + "clk26m",
> + "mainpll_d4_d4",
> + "mainpll_d4_d2",
> + "mainpll_d7",
> + "mainpll_d6",
> + "mainpll_d5"
> +};
> +
> +static const char * const dxcc_parents[] = {
> + "clk26m",
> + "mainpll_d4_d8",
> + "mainpll_d4_d4",
> + "mainpll_d4_d2"
> +};
> +
> +static const char * const apll_i2sin0_m_parents[] = {
> + "aud_1",
> + "aud_2"
> +};
All the audio interface clocks have the same set of parents. Please
have just one list.
[...]
Thanks
ChenYu
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