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Message-ID: <5f92b96a927c193232a3b11d96c3986448dd8dd2.camel@mediatek.com>
Date: Tue, 15 Jul 2025 08:13:21 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: "robh@...nel.org" <robh@...nel.org>, "mchehab@...nel.org"
<mchehab@...nel.org>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
"conor+dt@...nel.org" <conor+dt@...nel.org>, "matthias.bgg@...il.com"
<matthias.bgg@...il.com>, Shangyao Lin (林上堯)
<Shangyao.Lin@...iatek.com>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
CC: "linux-media@...r.kernel.org" <linux-media@...r.kernel.org>,
"linaro-mm-sig@...ts.linaro.org" <linaro-mm-sig@...ts.linaro.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@...iatek.com>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, "linux-mediatek@...ts.infradead.org"
<linux-mediatek@...ts.infradead.org>
Subject: Re: [PATCH v2 03/13] dt-bindings: media: mediatek: add cam-raw
binding
On Mon, 2025-07-07 at 09:31 +0800, shangyao lin wrote:
> From: "shangyao.lin" <shangyao.lin@...iatek.com>
>
> Add camera isp7x module device document.
>
> ---
[snip]
> +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml*__;Iw!!CTRNKA9wMg0ARbw!huoB5nm0-eewqNovfUlZpTbH1XdMjr0yWt3-_bNow3GppcMua0_ihDD4W1-due6CzcSdZJqTKs9hUNrWwljl0mM$
> +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!huoB5nm0-eewqNovfUlZpTbH1XdMjr0yWt3-_bNow3GppcMua0_ihDD4W1-due6CzcSdZJqTKs9hUNrWTOQ4FiY$
> +
> +title: The cam-raw unit of MediaTek ISP system
> +
> +maintainers:
> + - Shangyao Lin <shangyao.lin@...iatek.com>
> + - Shu-hsiang Yang <shu-hsiang.yang@...iatek.com>
> + - Shun-yi Wang <shun-yi.wang@...iatek.com>
> + - Teddy Chen <teddy.chen@...iatek.com>
> +
> +description:
> + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC.
After reading this description, I still don't understand what is cam-raw.
Describe more here.
What's the main function of it?
It has many iommu port, introduce the function of each port.
Regards,
CK
> +
> +properties:
> + compatible:
> + const: mediatek,mt8188-cam-raw
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + description:
> + Base address and optional inner base address of the cam-raw hardware block.
> +
> + reg-names:
> + items:
> + - const: base
> + - const: inner_base
> + minItems: 1
> + maxItems: 2
> + description:
> + Names for each register region. Must be "base" and optionally "inner_base".
> +
> + mediatek,larbs:
> + description:
> + List of phandles to the local arbiters in the current SoCs.
> + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml.
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + minItems: 1
> + maxItems: 32
> +
> + interrupts:
> + minItems: 1
> + description: Interrupts for the cam-raw block.
> +
> + dma-ranges:
> + minItems: 1
> + description: Address information of IOMMU mapping to memory.
> +
> + power-domains:
> + minItems: 1
> + description: Power domains for the cam-raw block.
> +
> + clocks:
> + minItems: 4
> + maxItems: 16
> + description: List of phandles to the clocks required by the cam-raw block.
> +
> + clock-names:
> + items:
> + - const: camsys_cam2mm0_cgpdn
> + - const: camsys_cam2mm1_cgpdn
> + - const: camsys_cam2sys_cgpdn
> + - const: camsys_cam_cgpdn
> + - const: camsys_camtg_cgpdn
> + - const: camsys_rawa_larbx_cgpdn
> + - const: camsys_rawa_cam_cgpdn
> + - const: camsys_rawa_camtg_cgpdn
> + - const: topckgen_top_cam
> + - const: topckgen_top_camtg
> + - const: topckgen_top_camtm
> + minItems: 4
> + maxItems: 16
> + description: Names of the clocks, must match the order of the clocks property.
> +
> + iommus:
> + minItems: 1
> + maxItems: 32
> + description: Points to the respective IOMMU block with master port as argument.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - power-domains
> + - clocks
> + - clock-names
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8188-power.h>
> + #include <dt-bindings/clock/mediatek,mt8188-clk.h>
> + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h>
> +
> + soc {
> + raw@...30000 {
> + compatible = "mediatek,mt8188-cam-raw";
> + reg = <0 0x16030000 0 0x8000>,
> + <0 0x16038000 0 0x8000>;
> + reg-names = "base", "inner_base";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>;
> + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>;
> + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>;
> + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>,
> + <&camsys CLK_CAM_MAIN_CAM>,
> + <&camsys CLK_CAM_MAIN_CAMTG>,
> + <&camsys_rawa CLK_CAM_RAWA_LARBX>,
> + <&camsys_rawa CLK_CAM_RAWA_CAM>,
> + <&camsys_rawa CLK_CAM_RAWA_CAMTG>,
> + <&topckgen CLK_TOP_CAM>,
> + <&topckgen CLK_TOP_CAMTG>,
> + <&topckgen CLK_TOP_CAMTM>;
> + clock-names = "camsys_cam2mm0_cgpdn",
> + "camsys_cam2mm1_cgpdn",
> + "camsys_cam2sys_cgpdn",
> + "camsys_cam_cgpdn",
> + "camsys_camtg_cgpdn",
> + "camsys_rawa_larbx_cgpdn",
> + "camsys_rawa_cam_cgpdn",
> + "camsys_rawa_camtg_cgpdn",
> + "topckgen_top_cam",
> + "topckgen_top_camtg",
> + "topckgen_top_camtm";
> + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_CQI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>,
> + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_AAI_R1>,
> + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>,
> + <&vpp_iommu M4U_PORT_L16A_FHO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_AAO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>,
> + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>;
> + };
> + };
> +
> +...
> \ No newline at end of file
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