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Message-ID: <b38cad0b-c2b1-44fc-847c-140066a12652@lunn.ch>
Date: Tue, 15 Jul 2025 15:24:50 +0200
From: Andrew Lunn <andrew@...n.ch>
To: "G Thomas, Rohan" <rohan.g.thomas@...era.com>
Cc: Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Serge Semin <fancer.lancer@...il.com>,
Romain Gantois <romain.gantois@...tlin.com>, netdev@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Matthew Gerlach <matthew.gerlach@...era.com>
Subject: Re: [PATCH net-next 1/3] net: stmmac: xgmac: Disable RX FIFO
Overflow interrupts
> > What is the reset default? Would it make sense to explicitly disable
> > it, rather than never enable it? What does 8a7cb245cf28 do?
>
> The RX FIFO Overflow interrupt is disabled by default on reset. Commit
> 8a7cb245cf28 also avoids enabling the interrupt rather than disabling
> it. This commit mirrors the same thing for the XGMAC IP.
So same as 8a7cb245cf28 is good.
When you resubmit with the correct Subject: please add Reviewed-by: Andrew Lunn <andrew@...n.ch>
Andrew
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