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Message-ID: <3exm3tytxfyc2f3vwah5gkxftibf2xrbzowe56gbgtk5j7as4j@ocnobxe7dspl>
Date: Wed, 16 Jul 2025 18:36:17 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: sboyd@...nel.org, mturquette@...libre.com, andersson@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
quic_rjendra@...cinc.com, taniya.das@....qualcomm.com,
linux-clk@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 5/7] clk: qcom: clk-alpha-pll: Add support for Taycan
EKO_T PLL
On Wed, Jul 16, 2025 at 08:50:15PM +0530, Pankaj Patil wrote:
> From: Taniya Das <taniya.das@....qualcomm.com>
>
> Add clock operations and register offsets to enable control of the Taycan
> EKO_T PLL, allowing for proper configuration and management of the PLL.
>
> Signed-off-by: Taniya Das <taniya.das@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
> drivers/clk/qcom/clk-alpha-pll.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
--
With best wishes
Dmitry
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