linux-kernel - [PATCH v3 1/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: add DSI & DSI PHY

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Message-ID: <20250716060114.52122-2-j-choudhary@ti.com>
Date: Wed, 16 Jul 2025 11:31:08 +0530
From: Jayesh Choudhary <j-choudhary@...com>
To: <nm@...com>, <vigneshr@...com>
CC: <kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>, <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <u-kumar1@...com>, <devarsht@...com>, <j-choudhary@...com>
Subject: [PATCH v3 1/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: add DSI & DSI PHY

Add DT nodes for DPI to DSI Bridge and DSI Phy. The DSI bridge
is Cadence DSI and the PHY is a Cadence DPHY with TI wrapper.

Signed-off-by: Jayesh Choudhary <j-choudhary@...com>
---
 .../dts/ti/k3-j784s4-j742s2-main-common.dtsi  | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 7c5b0c69897d..79d97d46b4c6 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -2522,6 +2522,45 @@ watchdog18: watchdog@...0000 {
 		status = "reserved";
 	};
 
+	dphy_tx0: phy@...0000 {
+		compatible = "ti,j721e-dphy";
+		reg = <0x00 0x04480000 0x00 0x00001000>;
+		clocks = <&k3_clks 402 20>, <&k3_clks 402 3>;
+		clock-names = "psm", "pll_ref";
+		#phy-cells = <0>;
+		power-domains = <&k3_pds 402 TI_SCI_PD_EXCLUSIVE>;
+		assigned-clocks = <&k3_clks 402 3>;
+		assigned-clock-parents = <&k3_clks 402 4>;
+		assigned-clock-rates = <19200000>;
+		status = "disabled";
+	};
+
+	dsi0: dsi@...0000 {
+		compatible = "ti,j721e-dsi";
+		reg = <0x00 0x04800000 0x00 0x00100000>,
+		      <0x00 0x04710000 0x00 0x00000100>;
+		clocks = <&k3_clks 215 2>, <&k3_clks 215 5>;
+		clock-names = "dsi_p_clk", "dsi_sys_clk";
+		power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
+		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&dphy_tx0>;
+		phy-names = "dphy";
+		status = "disabled";
+
+		dsi0_ports: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+			};
+
+			port@1 {
+				reg = <1>;
+			};
+		};
+	};
+
 	mhdp: bridge@...0000 {
 		compatible = "ti,j721e-mhdp8546";
 		reg = <0x0 0xa000000 0x0 0x30a00>,
-- 
2.34.1