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Message-ID: <20250716-wine-partridge-of-wonder-af10a6@krzk-bin>
Date: Wed, 16 Jul 2025 10:24:27 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jacky Chou <jacky_chou@...eedtech.com>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
joel@....id.au, andrew@...econstruct.com.au, linux-aspeed@...ts.ozlabs.org,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, openbmc@...ts.ozlabs.org, linux-gpio@...r.kernel.org,
linus.walleij@...aro.org, p.zabel@...gutronix.de, BMC-SW@...eedtech.com
Subject: Re: [PATCH v2 01/10] dt-bindings: soc: aspeed: Add ASPEED PCIe
Config support
On Tue, Jul 15, 2025 at 11:43:11AM +0800, Jacky Chou wrote:
> +maintainers:
> + - Jacky Chou <jacky_chou@...eedtech.com>
> +
> +description: |
Drop |
> + The ASPEED PCIe configuration syscon block provides a set of registers shared
> + by multiple PCIe-related devices within the SoC. This node represents the
> + common configuration space that allows these devices to coordinate and manage
> + shared PCIe settings, including address mapping, control, and status
> + registers. The syscon interface enables for various PCIe devices to access
> + and modify these shared registers in a consistent and centralized manner.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - aspeed,pcie-cfg
NAK, see writing bindings. You already received comments about generic
compatible in the past.
Best regards,
Krzysztof
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