| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20250717-dp_mst_bindings-v3-5-72ce08285703@oss.qualcomm.com>
Date: Thu, 17 Jul 2025 16:28:47 -0700
From: Jessica Zhang <jessica.zhang@....qualcomm.com>
To: Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <lumag@...nel.org>, Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Kuogee Hsieh <quic_khsieh@...cinc.com>,
Abel Vesa <abel.vesa@...aro.org>,
Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Mahadevan <quic_mahap@...cinc.com>,
Krishna Manikandan <quic_mkrishn@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>,
Rob Clark <robin.clark@....qualcomm.com>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Danila Tikhonov <danila@...xyga.com>,
cros-qcom-dts-watchers@...omium.org,
Rob Clark <robin.clark@....qualcomm.com>
Cc: Abhinav Kumar <abhinav.kumar@....qualcomm.com>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Yongxing Mou <quic_yongmou@...cinc.com>
Subject: [PATCH v3 5/5] arm64: dts: qcom: Add MST pixel streams for
displayport
The following chipsets support 2 total pixel streams:
- sa8775p (on mdss_dp1)
- sc8180x
- sc8280xp (mdss_dp0-2 only)
- sm8150
- sm8350
- sm8450
- sm8650
- x1e80100
The following chipset also supports 4 total pixel streams:
- sa8775p (mdss_dp0 only)
Add the appropriate amount of pixel stream clocks for their respective
displayport-controllers.
Signed-off-by: Jessica Zhang <jessica.zhang@....qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 34 ++++++++++++----
arch/arm64/boot/dts/qcom/sar2130p.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 20 +++++++---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 72 +++++++++++++++++++++++-----------
arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8450.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8550.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 +++--
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 30 +++++++++-----
12 files changed, 167 insertions(+), 69 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 45f536633f64..2c85eb2fc79a 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -4237,15 +4237,28 @@ mdss0_dp0: displayport-controller@...4000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel",
+ "stream_2_pixel",
+ "stream_3_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp0_phy 0>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>,
+ <&mdss0_dp0_phy 1>;
phys = <&mdss0_dp0_phy>;
phy-names = "dp";
@@ -4316,15 +4329,20 @@ mdss0_dp1: displayport-controller@...c000 {
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp1_phy 0>, <&mdss0_dp1_phy 1>;
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp1_phy 0>,
+ <&mdss0_dp1_phy 1>,
+ <&mdss0_dp1_phy 1>;
phys = <&mdss0_dp1_phy>;
phy-names = "dp";
diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
index b0e342810ae7..96090a948ade 100644
--- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi
@@ -2139,16 +2139,20 @@ mdss_dp0: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b1cc3bc1aec8..48b6a17dcea0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5012,15 +5012,19 @@ mdss_dp: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index b84e47a461a0..ca188c7f1f26 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -3233,16 +3233,20 @@ mdss_dp0: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>;
@@ -3311,16 +3315,20 @@ mdss_dp1: displayport-controller@...8000 {
<&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 87555a119d94..11ea2fa0b853 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -4338,15 +4338,19 @@ mdss0_dp0: displayport-controller@...0000 {
<&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4417,14 +4421,18 @@ mdss0_dp1: displayport-controller@...8000 {
<&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
@@ -4494,10 +4502,12 @@ mdss0_dp2: displayport-controller@...a000 {
<&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss0>;
interrupts = <14>;
phys = <&mdss0_dp2_phy>;
@@ -4505,8 +4515,11 @@ mdss0_dp2: displayport-controller@...a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss0_dp2_phy 0>,
+ <&mdss0_dp2_phy 1>,
+ <&mdss0_dp2_phy 1>;
operating-points-v2 = <&mdss0_dp2_opp_table>;
#sound-dai-cells = <0>;
@@ -5669,10 +5682,12 @@ mdss1_dp0: displayport-controller@...90000 {
<&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <12>;
phys = <&mdss1_dp0_phy>;
@@ -5680,8 +5695,11 @@ mdss1_dp0: displayport-controller@...90000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp0_phy 0>,
+ <&mdss1_dp0_phy 1>,
+ <&mdss1_dp0_phy 1>;
operating-points-v2 = <&mdss1_dp0_opp_table>;
#sound-dai-cells = <0>;
@@ -5741,10 +5759,12 @@ mdss1_dp1: displayport-controller@...98000 {
<&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <13>;
phys = <&mdss1_dp1_phy>;
@@ -5752,8 +5772,11 @@ mdss1_dp1: displayport-controller@...98000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp1_phy 0>,
+ <&mdss1_dp1_phy 1>,
+ <&mdss1_dp1_phy 1>;
operating-points-v2 = <&mdss1_dp1_opp_table>;
#sound-dai-cells = <0>;
@@ -5813,10 +5836,12 @@ mdss1_dp2: displayport-controller@...9a000 {
<&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface", "core_aux",
"ctrl_link",
- "ctrl_link_iface", "stream_pixel";
+ "ctrl_link_iface", "stream_pixel",
+ "stream_1_pixel";
interrupt-parent = <&mdss1>;
interrupts = <14>;
phys = <&mdss1_dp2_phy>;
@@ -5824,8 +5849,11 @@ mdss1_dp2: displayport-controller@...9a000 {
power-domains = <&rpmhpd SC8280XP_MMCX>;
assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
- assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
+ assigned-clock-parents = <&mdss1_dp2_phy 0>,
+ <&mdss1_dp2_phy 1>,
+ <&mdss1_dp2_phy 1>;
operating-points-v2 = <&mdss1_dp2_opp_table>;
#sound-dai-cells = <0>;
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index cdb47359c4c8..3a21a2e2c04d 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3894,16 +3894,20 @@ mdss_dp: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index f0d18fd37aaf..fc7c610c15d2 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -4774,16 +4774,20 @@ mdss_dp: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 971c828a7555..6a930292edd3 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2872,16 +2872,20 @@ mdss_dp: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 54c6d0fdb2af..b0680ef30c1f 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3431,16 +3431,20 @@ mdss_dp0: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 71a7e3b57ece..226c457338d9 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3545,16 +3545,20 @@ mdss_dp0: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 495ea9bfd008..72c63afe9029 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5388,16 +5388,20 @@ mdss_dp0: displayport-controller@...4000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&dp_opp_table>;
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a8eb4c5fe99f..e86b6cb20096 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5306,16 +5306,20 @@ mdss_dp0: displayport-controller@...0000 {
<&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp0_opp_table>;
@@ -5389,16 +5393,20 @@ mdss_dp1: displayport-controller@...8000 {
<&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp1_opp_table>;
@@ -5472,16 +5480,20 @@ mdss_dp2: displayport-controller@...a000 {
<&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
- <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
- "stream_pixel";
+ "stream_pixel",
+ "stream_1_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
- <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&mdss_dp2_opp_table>;
--
2.50.1
Powered by blists - more mailing lists