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Message-ID: <39b57899-4e8d-445f-a3b5-3b7f9ba3c3cb@tuxon.dev>
Date: Fri, 18 Jul 2025 09:45:02 +0300
From: Claudiu Beznea <claudiu.beznea@...on.dev>
To: Varshini Rajendran <varshini.rajendran@...rochip.com>,
mturquette@...libre.com, sboyd@...nel.org, nicolas.ferre@...rochip.com,
alexandre.belloni@...tlin.com, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: Patrice Vilchez <Patrice.Vilchez@...rochip.com>
Subject: Re: [PATCH v2] clk: at91: sam9x7: update pll clk ranges
On 14.07.2025 12:35, Varshini Rajendran wrote:
> Update the min, max ranges of the PLL clocks according to the latest
> datasheet to be coherent in the driver. This patch solves the issues in
> configuring the clocks related to peripherals with the desired frequency
> within the range.
>
> Fixes: 33013b43e271 ("clk: at91: sam9x7: add sam9x7 pmc driver")
> Suggested-by: Patrice Vilchez <Patrice.Vilchez@...rochip.com>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@...rochip.com>
Applied to clk-microchip, thanks!
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