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Message-ID: <13ca4d6e-d5db-4fd5-af14-9ccda55ddba2@quicinc.com>
Date: Fri, 18 Jul 2025 15:41:24 +0800
From: Luo Jie <quic_luoj@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Andrew Lunn
	<andrew+netdev@...n.ch>,
        "David S. Miller" <davem@...emloft.net>,
        "Eric
 Dumazet" <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>, Paolo Abeni
	<pabeni@...hat.com>,
        Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, Lei Wei
	<quic_leiwei@...cinc.com>,
        Suruchi Agarwal <quic_suruchia@...cinc.com>,
        Pavithra R <quic_pavir@...cinc.com>, Simon Horman <horms@...nel.org>,
        Jonathan Corbet <corbet@....net>, Kees Cook <kees@...nel.org>,
        "Gustavo A. R.
 Silva" <gustavoars@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>
CC: <linux-arm-msm@...r.kernel.org>, <netdev@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-doc@...r.kernel.org>, <linux-hardening@...r.kernel.org>,
        <quic_kkumarcs@...cinc.com>, <quic_linchen@...cinc.com>
Subject: Re: [PATCH net-next v5 10/14] net: ethernet: qualcomm: Initialize PPE
 RSS hash settings



On 7/18/2025 4:48 AM, Konrad Dybcio wrote:
> On 6/26/25 4:31 PM, Luo Jie wrote:
>> The PPE RSS hash is generated during PPE receive, based on the packet
>> content (3 tuples or 5 tuples) and as per the configured RSS seed. The
>> hash is then used to select the queue to transmit the packet to the
>> ARM CPU.
>>
>> This patch initializes the RSS hash settings that are used to generate
>> the hash for the packet during PPE packet receive.
>>
>> Signed-off-by: Luo Jie <quic_luoj@...cinc.com>
>> ---
>>   drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 194 ++++++++++++++++++++++++-
>>   drivers/net/ethernet/qualcomm/ppe/ppe_config.h |  39 +++++
>>   drivers/net/ethernet/qualcomm/ppe/ppe_regs.h   |  40 +++++
>>   3 files changed, 272 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
>> index dd7a4949f049..3b290eda7633 100644
>> --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
>> +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
>> @@ -1216,6 +1216,143 @@ int ppe_counter_enable_set(struct ppe_device *ppe_dev, int port)
>>   	return regmap_set_bits(ppe_dev->regmap, reg, PPE_PORT_EG_VLAN_TBL_TX_COUNTING_EN);
>>   }
>>   
>> +static int ppe_rss_hash_ipv4_config(struct ppe_device *ppe_dev, int index,
>> +				    struct ppe_rss_hash_cfg cfg)
>> +{
>> +	u32 reg, val;
>> +
>> +	switch (index) {
>> +	case 0:
>> +		val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_sip_mix[0]);
>> +		break;
>> +	case 1:
>> +		val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_dip_mix[0]);
>> +		break;
>> +	case 2:
>> +		val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_protocol_mix);
>> +		break;
>> +	case 3:
>> +		val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_dport_mix);
>> +		break;
>> +	case 4:
>> +		val = FIELD_PREP(PPE_RSS_HASH_MIX_IPV4_VAL, cfg.hash_sport_mix);
>> +		break;
>> +	default:
>> +		return -EINVAL;
>> +	}
>> +
>> +	reg = PPE_RSS_HASH_MIX_IPV4_ADDR + index * PPE_RSS_HASH_MIX_IPV4_INC;
>> +
>> +	return regmap_write(ppe_dev->regmap, reg, val);
> 
> FWIW you can assign the value in the switch statement and only FIELD_PREP
> it in the regmap_write, since the bitfield is the same
> 
> Konrad

Thank you for the suggestion, I'll update the code accordingly.


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