linux-kernel - [PATCH 3/3] arm64: dts: mediatek: mt8195: add UFSHCI node

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Message-ID: <20250718082719.653228-3-macpaul.lin@mediatek.com>
Date: Fri, 18 Jul 2025 16:27:18 +0800
From: Macpaul Lin <macpaul.lin@...iatek.com>
To: Alim Akhtar <alim.akhtar@...sung.com>, Avri Altman <avri.altman@....com>,
	Bart Van Assche <bvanassche@....org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	Matthias Brugger <matthias.bgg@...il.com>, AngeloGioacchino Del Regno
	<angelogioacchino.delregno@...labora.com>, Peter Wang
	<peter.wang@...iatek.com>, Stanley Jhu <chu.stanley@...il.com>, "James E . J
 . Bottomley" <James.Bottomley@...senPartnership.com>, "Martin K . Petersen"
	<martin.petersen@...cle.com>, <linux-scsi@...r.kernel.org>,
	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>,
	<openembedded-core@...ts.openembedded.org>, <patches@...ts.linux.dev>,
	<stable@...r.kernel.org>
CC: Bear Wang <bear.wang@...iatek.com>, Pablo Sun <pablo.sun@...iatek.com>,
	Ramax Lo <ramax.lo@...iatek.com>, Macpaul Lin <macpaul.lin@...iatek.com>,
	Macpaul Lin <macpaul@...il.com>, MediaTek Chromebook Upstream
	<Project_Global_Chrome_Upstream_Group@...iatek.com>, Rice Lee
	<ot_riceyj.lee@...iatek.com>, Eric Lin <ht.lin@...iatek.com>
Subject: [PATCH 3/3] arm64: dts: mediatek: mt8195: add UFSHCI node

From: Rice Lee <ot_riceyj.lee@...iatek.com>

Add a UFS host controller interface (UFSHCI) node to mt8195.dtsi.
Introduce the 'mediatek,ufs-disable-mcq' property to allow disabling
Multiple Circular Queue (MCQ) support.

Signed-off-by: Rice Lee <ot_riceyj.lee@...iatek.com>
Signed-off-by: Eric Lin <ht.lin@...iatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index dd065b1bf94a..8877953ce292 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1430,6 +1430,31 @@ mmc2: mmc@...50000 {
 			status = "disabled";
 		};
 
+		ufshci: ufshci@...70000 {
+			compatible = "mediatek,mt8195-ufshci";
+			reg = <0 0x11270000 0 0x2300>;
+			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&ufsphy>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>,
+				 <&infracfg_ao CLK_INFRA_AO_AES>,
+				 <&infracfg_ao CLK_INFRA_AO_UFS_TICK>,
+				 <&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>,
+				 <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>,
+				 <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>,
+				 <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>,
+				 <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>;
+			clock-names = "ufs", "ufs_aes", "ufs_tick",
+					"unipro_sysclk", "unipro_tick",
+					"unipro_mp_bclk", "ufs_tx_symbol",
+					"ufs_mem_sub";
+			freq-table-hz = <0 0>, <0 0>, <0 0>,
+					<0 0>, <0 0>, <0 0>,
+					<0 0>, <0 0>;
+
+			mediatek,ufs-disable-mcq;
+			status = "disabled";
+		};
+
 		lvts_mcu: thermal-sensor@...78000 {
 			compatible = "mediatek,mt8195-lvts-mcu";
 			reg = <0 0x11278000 0 0x1000>;
-- 
2.45.2