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Message-ID: <CAMvTesDMsV=0Z-W5V9uOTM8WBjyqs0dMLxdEkjpVYFgR6Wojag@mail.gmail.com>
Date: Fri, 18 Jul 2025 09:45:05 +0800
From: Tianyu Lan <ltykernel@...il.com>
To: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
Cc: linux-kernel@...r.kernel.org, bp@...en8.de, tglx@...utronix.de,
mingo@...hat.com, dave.hansen@...ux.intel.com, Thomas.Lendacky@....com,
nikunj@....com, Santosh.Shukla@....com, Vasant.Hegde@....com,
Suravee.Suthikulpanit@....com, David.Kaplan@....com, x86@...nel.org,
hpa@...or.com, peterz@...radead.org, seanjc@...gle.com, pbonzini@...hat.com,
kvm@...r.kernel.org, kirill.shutemov@...ux.intel.com, huibo.wang@....com,
naveen.rao@....com, kai.huang@...el.com
Subject: Re: [RFC PATCH v8 24/35] x86/apic: Add support to send IPI for Secure AVIC
On Wed, Jul 9, 2025 at 11:42 AM Neeraj Upadhyay <Neeraj.Upadhyay@....com> wrote:
>
> With Secure AVIC only Self-IPI is accelerated. To handle all the
> other IPIs, add new callbacks for sending IPI. These callbacks write
> to the IRR of the target guest vCPU's APIC backing page and issue
> GHCB protocol MSR write event for the hypervisor to notify the
> target vCPU about the new interrupt request.
>
> For Secure AVIC GHCB APIC MSR writes, reuse GHCB msr handling code in
> vc_handle_msr() by exposing a sev-internal sev_es_ghcb_handle_msr().
>
> Co-developed-by: Kishon Vijay Abraham I <kvijayab@....com>
> Signed-off-by: Kishon Vijay Abraham I <kvijayab@....com>
> Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@....com>
> ---
> Changes since v7:
> - No change.
Reviewed-by: Tianyu Lan <tiala@...rosoft.com>
--
Thanks
Tianyu Lan
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