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Message-ID: <650ff5407528b8a90867ff1ac072b4112c91c866.1752837842.git.michal.simek@amd.com>
Date: Fri, 18 Jul 2025 13:24:07 +0200
From: Michal Simek <michal.simek@....com>
To: <linux-kernel@...r.kernel.org>, <monstr@...str.eu>,
<michal.simek@...inx.com>, <git@...inx.com>
CC: Conor Dooley <conor+dt@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>, "open list:OPEN FIRMWARE
AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, "moderated
list:ARM/ZYNQ ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH 2/3] arm64: zynqmp: Add support for kr260 board
The kit based on K26 SOM is built for robotics and industrial application.
Signed-off-by: Michal Simek <michal.simek@....com>
---
https://www.amd.com/en/products/system-on-modules/kria/k26/kr260-robotics-starter-kit.html
---
arch/arm64/boot/dts/xilinx/Makefile | 9 +
.../boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 438 +++++++++++++++++
.../boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 451 ++++++++++++++++++
3 files changed, 898 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 7f5a8801cad1..5e84e3c725e2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -30,4 +30,13 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb
zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb
+zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revA.dtb
+zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kr-g-revB.dtb
+zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revA.dtb
+zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kr-g-revB.dtb
+
dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
new file mode 100644
index 000000000000..fbacfa984d76
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KR260 revA Carrier Card
+ *
+ * (C) Copyright 2021, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@....com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sk-kr260-revA",
+ "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
+ model = "ZynqMP KR260 revA";
+
+ aliases {
+ ethernet0 = "/axi/ethernet@...b0000"; /* &gem0 */
+ ethernet1 = "/axi/ethernet@...c0000"; /* &gem1 */
+ };
+
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ clk_27: clock0 { /* u86 - DP */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clk_125: si5332-0 { /* u17 - GEM0/1 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_74: si5332-5 { /* u17 - SLVC-EC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ clk_26: si5332-2 { /* u17 - USB */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk_156: si5332-3 { /* u17 - SFP+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+
+ clk_25_0: si5332-1 { /* u17 - GEM2 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ clk_25_1: si5332-4 { /* u17 - GEM3 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+};
+
+&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+
+ slg7xl45106: gpio@11 { /* u19 - reset logic */
+ compatible = "dlg,slg7xl45106";
+ reg = <0x11>;
+ label = "resetchip";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
+ "SD_RESET_B", "USB0_HUB_RESET_B",
+ "USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
+ "PS_GEM1_RESET_B", "";
+ };
+
+ i2c-mux@74 { /* u18 */
+ compatible = "nxp,pca9546";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ usbhub_i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ hub_1: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
+ };
+ usbhub_i2c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ hub_2: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
+ };
+ /* Bus 2/3 are not connected */
+ };
+
+ /* si5332@6a - u17 - clock-generator */
+};
+
+/* GEM SGMII/DP and USB 3.0 */
+&psgtr {
+ status = "okay";
+ /* gem0/1, dp, usb */
+ clocks = <&clk_125>, <&clk_27>, <&clk_26>;
+ clock-names = "ref0", "ref1", "ref2";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
+ assigned-clock-rates = <27000000>, <25000000>, <300000000>;
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+ assigned-clock-rates = <600000000>;
+};
+
+&usb0 { /* mio52 - mio63 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+ reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
+ assigned-clock-rates = <250000000>, <20000000>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&usb1 { /* mio64 - mio75 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
+ reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
+ assigned-clock-rates = <250000000>, <20000000>;
+};
+
+&dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub1_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub1_3_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub1_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub1_2_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gem0 { /* mdio mio50/51 */
+ status = "okay";
+ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ assigned-clock-rates = <250000000>;
+};
+
+&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ assigned-clock-rates = <250000000>;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@4 { /* u81 */
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <4>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-assert-us = <300>;
+ reset-deassert-us = <280>;
+ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
+ };
+ phy1: ethernet-phy@8 { /* u36 */
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <8>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-assert-us = <100>;
+ reset-deassert-us = <280>;
+ reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* gem2/gem3 via PL with phys u79@2 and u80@3 */
+
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ output-enable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO44", "MIO46", "MIO48";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO45", "MIO47", "MIO49";
+ bias-disable;
+ output-enable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40",
+ "MIO41", "MIO42", "MIO43";
+ bias-disable;
+ output-enable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ output-enable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ conf {
+ groups = "usb1_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
new file mode 100644
index 000000000000..b7cda216b179
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso
@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KR260 revB Carrier Card (A03 revision)
+ *
+ * (C) Copyright 2021 - 2022, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@....com>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+ compatible = "xlnx,zynqmp-sk-kr260-revB",
+ "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
+ model = "ZynqMP KR260 revB";
+
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ clk_125: clock0 { /* u87 - GEM0/1 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk_27: clock1 { /* u86 - DP */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clk_26: clock2 { /* u89 - USB */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clk_156: clock3 { /* u90 - SFP+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <156250000>;
+ };
+
+ clk_25_0: clock4 { /* u92/u91 - GEM2 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ clk_25_1: clock5 { /* u92/u91 - GEM3 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ clk_74: clock6 { /* u88 - SLVC-EC */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <74250000>;
+ };
+
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
+};
+
+&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+
+ slg7xl45106: gpio@11 { /* u19 - reset logic */
+ compatible = "dlg,slg7xl45106";
+ reg = <0x11>;
+ label = "resetchip";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
+ "SD_RESET_B", "USB0_HUB_RESET_B",
+ "USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
+ "PS_GEM1_RESET_B", "";
+ };
+
+ i2c-mux@74 { /* u18 */
+ compatible = "nxp,pca9546";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ usbhub_i2c0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ hub_1: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
+ };
+ usbhub_i2c1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ hub_2: usb-hub@2d {
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ };
+ };
+ /* Bus 2/3 are not connected */
+ };
+
+ /* si5332@6a - u17 - clock-generator */
+};
+
+/* GEM SGMII/DP and USB 3.0 */
+&psgtr {
+ status = "okay";
+ /* gem0/1, dp, usb */
+ clocks = <&clk_125>, <&clk_27>, <&clk_26>;
+ clock-names = "ref0", "ref1", "ref2";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
+ assigned-clock-rates = <27000000>, <25000000>, <300000000>;
+};
+
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+ assigned-clock-rates = <600000000>;
+};
+
+&usb0 { /* mio52 - mio63 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+ reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
+ assigned-clock-rates = <250000000>, <20000000>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub_3_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub_2_0>;
+ i2c-bus = <&hub_1>;
+ reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&usb1 { /* mio64 - mio75 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
+ reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
+ assigned-clock-rates = <250000000>, <20000000>;
+};
+
+&dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub1_2_0: hub@1 {
+ compatible = "usb424,2744";
+ reg = <1>;
+ peer-hub = <&hub1_3_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub1_3_0: hub@2 {
+ compatible = "usb424,5744";
+ reg = <2>;
+ peer-hub = <&hub1_2_0>;
+ i2c-bus = <&hub_2>;
+ reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&gem0 { /* mdio mio50/51 */
+ status = "okay";
+ phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii";
+ assigned-clock-rates = <250000000>;
+};
+
+&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ assigned-clock-rates = <250000000>;
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@4 { /* u81 */
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <4>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-assert-us = <300>;
+ reset-deassert-us = <280>;
+ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
+ };
+ phy1: ethernet-phy@8 { /* u36 */
+ #phy-cells = <1>;
+ compatible = "ethernet-phy-id2000.a231";
+ reg = <8>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ reset-assert-us = <100>;
+ reset-deassert-us = <280>;
+ reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+/* gem2/gem3 via PL with phys u79@2 and u80@3 */
+
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ output-enable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO44", "MIO46", "MIO48";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO45", "MIO47", "MIO49";
+ bias-disable;
+ output-enable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40",
+ "MIO41", "MIO42", "MIO43";
+ bias-disable;
+ output-enable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ output-enable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ conf {
+ groups = "usb1_0_grp";
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ drive-strength = <12>;
+ slew-rate = <SLEW_RATE_FAST>;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ output-enable;
+ drive-strength = <4>;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
--
2.43.0
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