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Message-Id: <20250721-dr1v90-basic-dt-v1-7-5740c5199c47@pigmoral.tech> Date: Mon, 21 Jul 2025 23:46:13 +0800 From: Junhui Liu <junhui.liu@...moral.tech> To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>, Daniel Lezcano <daniel.lezcano@...aro.org>, Thomas Gleixner <tglx@...utronix.de>, Samuel Holland <samuel.holland@...ive.com>, Anup Patel <anup@...infault.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Jiri Slaby <jirislaby@...nel.org> Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, Palmer Dabbelt <palmer@...ive.com>, Conor Dooley <conor@...nel.org>, linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org, Junhui Liu <junhui.liu@...moral.tech> Subject: [PATCH RFC 07/10] riscv: Add Anlogic SoC famly Kconfig support The first SoC in the Anlogic series is DR1V90, which contains a RISC-V core from Nuclei. Signed-off-by: Junhui Liu <junhui.liu@...moral.tech> --- arch/riscv/Kconfig.socs | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a9c3d2f6debca1469f4a912b3414711eb709baab..de163cdddcda1c08e7c9e98716eaf043d4c4555a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,10 @@ menu "SoC selection" +config ARCH_ANLOGIC + bool "Anlogic SoCs" + help + This enables support for Anlogic SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP -- 2.50.1
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