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Message-Id: <20250720-t210b01-v2-7-9cb209f1edfc@gmail.com>
Date: Sun, 20 Jul 2025 21:15:01 -0500
From: Aaron Kling via B4 Relay <devnull+webgeek1234.gmail.com@...nel.org>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Jonathan Hunter <jonathanh@...dia.com>, Vinod Koul <vkoul@...nel.org>,
Kishon Vijay Abraham I <kishon@...nel.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Nagarjuna Kristam <nkristam@...dia.com>, JC Kuo <jckuo@...dia.com>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>, Zhang Rui <rui.zhang@...el.com>,
Lukasz Luba <lukasz.luba@....com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Mathias Nyman <mathias.nyman@...el.com>,
Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>
Cc: devicetree@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
linux-usb@...r.kernel.org, Thierry Reding <treding@...dia.com>,
linux-pm@...r.kernel.org, linux-clk@...r.kernel.org,
Aaron Kling <webgeek1234@...il.com>
Subject: [PATCH v2 07/17] dt-bindings: clock: tegra124-dfll: Document
Tegra210B01
From: Aaron Kling <webgeek1234@...il.com>
Add Tegra210B01 support for DFLL clock.
Acked-by: Rob Herring (Arm) <robh@...nel.org>
Signed-off-by: Aaron Kling <webgeek1234@...il.com>
---
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
index f7d347385b5775ddd702ecbb9821acfc9d4b9ff2..aa7d50d4fe6f2c1c2500c53e3421355ce2b67599 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
@@ -13,6 +13,7 @@ Required properties:
- compatible : should be one of:
- "nvidia,tegra124-dfll": for Tegra124
- "nvidia,tegra210-dfll": for Tegra210
+ - "nvidia,tegra210b01-dfll": for Tegra210B01
- reg : Defines the following set of registers, in the order listed:
- registers for the DFLL control logic.
- registers for the I2C output logic.
--
2.50.1
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