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Message-ID: <468961ac17fb5dd4365943a24206040575b0e982.camel@pengutronix.de>
Date: Mon, 21 Jul 2025 13:02:54 +0200
From: Philipp Zabel <p.zabel@...gutronix.de>
To: Ze Huang <huang.ze@...ux.dev>, Greg Kroah-Hartman
<gregkh@...uxfoundation.org>, Rob Herring <robh@...nel.org>, Krzysztof
Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Yixun
Lan <dlan@...too.org>, Thinh Nguyen <Thinh.Nguyen@...opsys.com>
Cc: linux-usb@...r.kernel.org, devicetree@...r.kernel.org,
linux-riscv@...ts.infradead.org, spacemit@...ts.linux.dev,
linux-kernel@...r.kernel.org, Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH v6 1/2] dt-bindings: usb: dwc3: add support for SpacemiT
K1
On Sa, 2025-07-12 at 15:49 +0800, Ze Huang wrote:
> Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> in the SpacemiT K1 SoC. The controller is based on the Synopsys
> DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
> DRD mode.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Signed-off-by: Ze Huang <huang.ze@...ux.dev>
> ---
> .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml | 107 +++++++++++++++++++++
> 1 file changed, 107 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..c967ad6aae50199127a4f8a17d53fc34e8d9480b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> @@ -0,0 +1,107 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
> +
> +maintainers:
> + - Ze Huang <huang.ze@...ux.dev>
> +
> +description: |
> + The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
> + for USB 3.0 and DRD for USB 2.0.
> +
> + Key features:
> + - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
> + - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
> + - Internal DMA controller and flexible endpoint FIFO sizing
> +
> + Communication Interface:
> + - Use of PIPE3 (125MHz) interface for USB3.0 PHY
> + - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
> +
> +allOf:
> + - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> + compatible:
> + const: spacemit,k1-dwc3
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: usbdrd30
> +
> + interrupts:
> + maxItems: 1
> +
> + phys:
> + items:
> + - description: phandle to USB2/HS PHY
> + - description: phandle to USB3/SS PHY
> +
> + phy-names:
> + items:
> + - const: usb2-phy
> + - const: usb3-phy
> +
> + resets:
> + items:
> + - description: USB3.0 AHB reset line
> + - description: USB3.0 VCC reset line
> + - description: USB3.0 PHY reset line
Are we sure all resets will only ever need to be triggered together?
Otherwise it might be safer to add a reset-names property.
regards
Philipp
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