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Message-ID: <20250722-proposal-gothic-e0c3725e0874@spud>
Date: Tue, 22 Jul 2025 16:21:21 +0100
From: Conor Dooley <conor@...nel.org>
To: Junhui Liu <junhui.liu@...moral.tech>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Samuel Holland <samuel.holland@...ive.com>,
Anup Patel <anup@...infault.org>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Jiri Slaby <jirislaby@...nel.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Palmer Dabbelt <palmer@...ive.com>,
linux-riscv@...ts.infradead.org, linux-serial@...r.kernel.org
Subject: Re: [PATCH RFC 08/10] riscv: dts: Add initial Anlogic DR1V90 SoC
device tree
On Mon, Jul 21, 2025 at 11:46:14PM +0800, Junhui Liu wrote:
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + timebase-frequency = <800000000>;
> +
> + cpu@0 {
> + compatible = "nuclei,ux900", "riscv";
> + device_type = "cpu";
> + reg = <0>;
> + riscv,isa = "rv64imafdc";
> + riscv,isa-base = "rv64i";
> + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zbc",
> + "zbkc", "zbs", "zicntr", "zicsr", "zifencei",
> + "zihintpause", "zihpm";
Why do riscv,isa and riscv,isa-extensions differ?
If riscv,isa is not even accurate, why not just remove it entirely?
> + i-cache-block-size = <64>;
> + i-cache-size = <32768>;
> + i-cache-sets = <256>;
> + d-cache-block-size = <64>;
> + d-cache-size = <32768>;
> + d-cache-sets = <256>;
> + mmu-type = "riscv,sv39";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
> + };
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